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@@ -26,6 +26,7 @@
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/* SGMII digital lane registers */
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#define EMAC_SGMII_LN_DRVR_CTRL0 0x000C
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+#define EMAC_SGMII_LN_DRVR_CTRL1 0x0010
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#define EMAC_SGMII_LN_DRVR_TAP_EN 0x0018
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#define EMAC_SGMII_LN_TX_MARGINING 0x001C
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#define EMAC_SGMII_LN_TX_PRE 0x0020
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@@ -48,6 +49,7 @@
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#define EMAC_SGMII_LN_RX_EN_SIGNAL 0x02AC
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#define EMAC_SGMII_LN_RX_MISC_CNTRL0 0x02B8
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#define EMAC_SGMII_LN_DRVR_LOGIC_CLKDIV 0x02C8
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+#define EMAC_SGMII_LN_RX_RESECODE_OFFSET 0x02CC
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/* SGMII digital lane register values */
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#define UCDR_STEP_BY_TWO_MODE0 BIT(7)
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@@ -73,6 +75,8 @@
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#define CML_GEAR_MODE(x) (((x) & 7) << 3)
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#define CML2CMOS_IBOOST_MODE(x) ((x) & 7)
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+#define RESCODE_OFFSET(x) ((x) & 0x1f)
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+
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#define MIXER_LOADB_MODE(x) (((x) & 0xf) << 2)
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#define MIXER_DATARATE_MODE(x) ((x) & 3)
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@@ -159,6 +163,8 @@ static const struct emac_reg_write sgmii_laned[] = {
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{EMAC_SGMII_LN_PARALLEL_RATE, PARALLEL_RATE_MODE0(1)},
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{EMAC_SGMII_LN_TX_BAND_MODE, BAND_MODE0(1)},
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{EMAC_SGMII_LN_RX_BAND, BAND_MODE0(2)},
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+ {EMAC_SGMII_LN_DRVR_CTRL1, RESCODE_OFFSET(7)},
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+ {EMAC_SGMII_LN_RX_RESECODE_OFFSET, RESCODE_OFFSET(9)},
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{EMAC_SGMII_LN_LANE_MODE, LANE_MODE(26)},
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{EMAC_SGMII_LN_RX_RCVR_PATH1_MODE0, CDR_PD_SEL_MODE0(2) |
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EN_DLL_MODE0 | EN_IQ_DCC_MODE0 | EN_IQCAL_MODE0},
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