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@@ -19,6 +19,7 @@
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struct cmux_clk {
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struct clk_hw hw;
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void __iomem *reg;
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+ unsigned int clk_per_pll;
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u32 flags;
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};
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@@ -27,14 +28,12 @@ struct cmux_clk {
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#define CLKSEL_ADJUST BIT(0)
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#define to_cmux_clk(p) container_of(p, struct cmux_clk, hw)
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-static unsigned int clocks_per_pll;
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-
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static int cmux_set_parent(struct clk_hw *hw, u8 idx)
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{
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struct cmux_clk *clk = to_cmux_clk(hw);
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u32 clksel;
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- clksel = ((idx / clocks_per_pll) << 2) + idx % clocks_per_pll;
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+ clksel = ((idx / clk->clk_per_pll) << 2) + idx % clk->clk_per_pll;
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if (clk->flags & CLKSEL_ADJUST)
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clksel += 8;
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clksel = (clksel & 0xf) << CLKSEL_SHIFT;
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@@ -52,7 +51,7 @@ static u8 cmux_get_parent(struct clk_hw *hw)
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clksel = (clksel >> CLKSEL_SHIFT) & 0xf;
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if (clk->flags & CLKSEL_ADJUST)
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clksel -= 8;
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- clksel = (clksel >> 2) * clocks_per_pll + clksel % 4;
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+ clksel = (clksel >> 2) * clk->clk_per_pll + clksel % 4;
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return clksel;
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}
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@@ -72,6 +71,7 @@ static void __init core_mux_init(struct device_node *np)
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u32 offset;
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const char *clk_name;
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const char **parent_names;
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+ struct of_phandle_args clkspec;
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rc = of_property_read_u32(np, "reg", &offset);
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if (rc) {
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@@ -105,6 +105,17 @@ static void __init core_mux_init(struct device_node *np)
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goto err_clk;
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}
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+ rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0,
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+ &clkspec);
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+ if (rc) {
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+ pr_err("%s: parse clock node error\n", __func__);
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+ goto err_clk;
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+ }
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+
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+ cmux_clk->clk_per_pll = of_property_count_strings(clkspec.np,
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+ "clock-output-names");
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+ of_node_put(clkspec.np);
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+
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node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen");
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if (node && (offset >= 0x80))
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cmux_clk->flags = CLKSEL_ADJUST;
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@@ -181,9 +192,6 @@ static void __init core_pll_init(struct device_node *np)
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goto err_map;
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}
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- /* output clock number per PLL */
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- clocks_per_pll = count;
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-
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subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL);
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if (!subclks) {
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pr_err("%s: could not allocate subclks\n", __func__);
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