|
@@ -78,19 +78,6 @@ enum b43_nphy_rssi_type {
|
|
|
B43_NPHY_RSSI_TBD,
|
|
|
};
|
|
|
|
|
|
-/* TODO: reorder functions */
|
|
|
-static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
|
|
|
- bool enable);
|
|
|
-static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
|
|
|
- u8 *events, u8 *delays, u8 length);
|
|
|
-static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
|
|
|
- enum b43_nphy_rf_sequence seq);
|
|
|
-static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
|
|
|
- u16 value, u8 core, bool off);
|
|
|
-static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
|
|
|
- u16 value, u8 core);
|
|
|
-static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev);
|
|
|
-
|
|
|
static inline bool b43_nphy_ipa(struct b43_wldev *dev)
|
|
|
{
|
|
|
enum ieee80211_band band = b43_current_band(dev->wl);
|
|
@@ -98,638 +85,573 @@ static inline bool b43_nphy_ipa(struct b43_wldev *dev)
|
|
|
(dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
|
|
|
}
|
|
|
|
|
|
-void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
|
|
|
-{//TODO
|
|
|
-}
|
|
|
-
|
|
|
-static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
|
|
|
-{//TODO
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
|
|
|
+static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
|
|
|
+ if (dev->phy.rev >= 6) {
|
|
|
+ if (dev->dev->chip_id == 47162)
|
|
|
+ return txpwrctrl_tx_gain_ipa_rev5;
|
|
|
+ return txpwrctrl_tx_gain_ipa_rev6;
|
|
|
+ } else if (dev->phy.rev >= 5) {
|
|
|
+ return txpwrctrl_tx_gain_ipa_rev5;
|
|
|
+ } else {
|
|
|
+ return txpwrctrl_tx_gain_ipa;
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ return txpwrctrl_tx_gain_ipa_5g;
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
-static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
|
|
|
- bool ignore_tssi)
|
|
|
-{//TODO
|
|
|
- return B43_TXPWR_RES_DONE;
|
|
|
-}
|
|
|
+/**************************************************
|
|
|
+ * RF (just without b43_nphy_rf_control_intc_override)
|
|
|
+ **************************************************/
|
|
|
|
|
|
-static void b43_chantab_radio_upload(struct b43_wldev *dev,
|
|
|
- const struct b43_nphy_channeltab_entry_rev2 *e)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
|
|
|
+static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
|
|
|
+ enum b43_nphy_rf_sequence seq)
|
|
|
{
|
|
|
- b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
|
|
|
- b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
|
|
|
- b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
|
|
|
- b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
|
|
|
- b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
|
|
|
+ static const u16 trigger[] = {
|
|
|
+ [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
|
|
|
+ [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
|
|
|
+ [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
|
|
|
+ [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
|
|
|
+ [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
|
|
|
+ [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
|
|
|
+ };
|
|
|
+ int i;
|
|
|
+ u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
|
|
|
|
|
|
- b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
|
|
|
- b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
|
|
|
- b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
|
|
|
- b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
|
|
|
- b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
|
|
|
+ B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
|
|
|
|
|
|
- b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
|
|
|
- b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
|
|
|
- b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
|
|
|
- b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
|
|
|
- b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
|
|
|
+ b43_phy_set(dev, B43_NPHY_RFSEQMODE,
|
|
|
+ B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
|
|
|
+ b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
|
|
|
+ for (i = 0; i < 200; i++) {
|
|
|
+ if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
|
|
|
+ goto ok;
|
|
|
+ msleep(1);
|
|
|
+ }
|
|
|
+ b43err(dev->wl, "RF sequence status timeout\n");
|
|
|
+ok:
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
|
|
|
+}
|
|
|
|
|
|
- b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
|
|
|
- b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
|
|
|
- b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
|
|
|
- b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
|
|
|
- b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
|
|
|
+static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
|
|
|
+ u16 value, u8 core, bool off)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+ u8 index = fls(field);
|
|
|
+ u8 addr, en_addr, val_addr;
|
|
|
+ /* we expect only one bit set */
|
|
|
+ B43_WARN_ON(field & (~(1 << (index - 1))));
|
|
|
|
|
|
- b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
|
|
|
- b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
|
|
|
- b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
|
|
|
- b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
|
|
|
- b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ const struct nphy_rf_control_override_rev3 *rf_ctrl;
|
|
|
+ for (i = 0; i < 2; i++) {
|
|
|
+ if (index == 0 || index == 16) {
|
|
|
+ b43err(dev->wl,
|
|
|
+ "Unsupported RF Ctrl Override call\n");
|
|
|
+ return;
|
|
|
+ }
|
|
|
|
|
|
- b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
|
|
|
- b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
|
|
|
-}
|
|
|
+ rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
|
|
|
+ en_addr = B43_PHY_N((i == 0) ?
|
|
|
+ rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
|
|
|
+ val_addr = B43_PHY_N((i == 0) ?
|
|
|
+ rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
|
|
|
|
|
|
-static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
|
|
|
- const struct b43_nphy_channeltab_entry_rev3 *e)
|
|
|
-{
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
|
|
|
- e->radio_syn_pll_loopfilter1);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
|
|
|
- e->radio_syn_pll_loopfilter2);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
|
|
|
- e->radio_syn_pll_loopfilter3);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
|
|
|
- e->radio_syn_pll_loopfilter4);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
|
|
|
- e->radio_syn_pll_loopfilter5);
|
|
|
- b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
|
|
|
- e->radio_syn_reserved_addr27);
|
|
|
- b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
|
|
|
- e->radio_syn_reserved_addr28);
|
|
|
- b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
|
|
|
- e->radio_syn_reserved_addr29);
|
|
|
- b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
|
|
|
- e->radio_syn_logen_vcobuf1);
|
|
|
- b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
|
|
|
- b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
|
|
|
- b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
|
|
|
+ if (off) {
|
|
|
+ b43_phy_mask(dev, en_addr, ~(field));
|
|
|
+ b43_phy_mask(dev, val_addr,
|
|
|
+ ~(rf_ctrl->val_mask));
|
|
|
+ } else {
|
|
|
+ if (core == 0 || ((1 << core) & i) != 0) {
|
|
|
+ b43_phy_set(dev, en_addr, field);
|
|
|
+ b43_phy_maskset(dev, val_addr,
|
|
|
+ ~(rf_ctrl->val_mask),
|
|
|
+ (value << rf_ctrl->val_shift));
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ const struct nphy_rf_control_override_rev2 *rf_ctrl;
|
|
|
+ if (off) {
|
|
|
+ b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
|
|
|
+ value = 0;
|
|
|
+ } else {
|
|
|
+ b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
|
|
|
+ }
|
|
|
|
|
|
- b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
|
|
|
- e->radio_rx0_lnaa_tune);
|
|
|
- b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
|
|
|
- e->radio_rx0_lnag_tune);
|
|
|
+ for (i = 0; i < 2; i++) {
|
|
|
+ if (index <= 1 || index == 16) {
|
|
|
+ b43err(dev->wl,
|
|
|
+ "Unsupported RF Ctrl Override call\n");
|
|
|
+ return;
|
|
|
+ }
|
|
|
|
|
|
- b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
|
|
|
- e->radio_tx0_intpaa_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
|
|
|
- e->radio_tx0_intpag_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
|
|
|
- e->radio_tx0_pada_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
|
|
|
- e->radio_tx0_padg_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
|
|
|
- e->radio_tx0_pgaa_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
|
|
|
- e->radio_tx0_pgag_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
|
|
|
- e->radio_tx0_mixa_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
|
|
|
- e->radio_tx0_mixg_boost_tune);
|
|
|
+ if (index == 2 || index == 10 ||
|
|
|
+ (index >= 13 && index <= 15)) {
|
|
|
+ core = 1;
|
|
|
+ }
|
|
|
|
|
|
- b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
|
|
|
- e->radio_rx1_lnaa_tune);
|
|
|
- b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
|
|
|
- e->radio_rx1_lnag_tune);
|
|
|
+ rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
|
|
|
+ addr = B43_PHY_N((i == 0) ?
|
|
|
+ rf_ctrl->addr0 : rf_ctrl->addr1);
|
|
|
|
|
|
- b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
|
|
|
- e->radio_tx1_intpaa_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
|
|
|
- e->radio_tx1_intpag_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
|
|
|
- e->radio_tx1_pada_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
|
|
|
- e->radio_tx1_padg_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
|
|
|
- e->radio_tx1_pgaa_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
|
|
|
- e->radio_tx1_pgag_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
|
|
|
- e->radio_tx1_mixa_boost_tune);
|
|
|
- b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
|
|
|
- e->radio_tx1_mixg_boost_tune);
|
|
|
+ if ((core & (1 << i)) != 0)
|
|
|
+ b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
|
|
|
+ (value << rf_ctrl->shift));
|
|
|
+
|
|
|
+ b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
|
|
|
+ b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
|
|
+ B43_NPHY_RFCTL_CMD_START);
|
|
|
+ udelay(1);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
|
|
|
+ }
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
|
|
|
-static void b43_radio_2056_setup(struct b43_wldev *dev,
|
|
|
- const struct b43_nphy_channeltab_entry_rev3 *e)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
|
|
|
+static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
|
|
|
+ u16 value, u8 core)
|
|
|
{
|
|
|
- struct ssb_sprom *sprom = dev->dev->bus_sprom;
|
|
|
- enum ieee80211_band band = b43_current_band(dev->wl);
|
|
|
- u16 offset;
|
|
|
- u8 i;
|
|
|
- u16 bias, cbias, pag_boost, pgag_boost, mixg_boost, padg_boost;
|
|
|
+ u8 i, j;
|
|
|
+ u16 reg, tmp, val;
|
|
|
|
|
|
B43_WARN_ON(dev->phy.rev < 3);
|
|
|
+ B43_WARN_ON(field > 4);
|
|
|
|
|
|
- b43_chantab_radio_2056_upload(dev, e);
|
|
|
- b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
|
|
|
+ for (i = 0; i < 2; i++) {
|
|
|
+ if ((core == 1 && i == 1) || (core == 2 && !i))
|
|
|
+ continue;
|
|
|
|
|
|
- if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
|
|
|
- b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
|
|
|
- if (dev->dev->chip_id == 0x4716) {
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
|
|
|
- } else {
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
|
|
|
- }
|
|
|
- }
|
|
|
- if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
|
|
|
- b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
|
|
|
- }
|
|
|
-
|
|
|
- if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- offset = i ? B2056_TX1 : B2056_TX0;
|
|
|
- if (dev->phy.rev >= 5) {
|
|
|
- b43_radio_write(dev,
|
|
|
- offset | B2056_TX_PADG_IDAC, 0xcc);
|
|
|
+ reg = (i == 0) ?
|
|
|
+ B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
|
|
|
+ b43_phy_mask(dev, reg, 0xFBFF);
|
|
|
|
|
|
- if (dev->dev->chip_id == 0x4716) {
|
|
|
- bias = 0x40;
|
|
|
- cbias = 0x45;
|
|
|
- pag_boost = 0x5;
|
|
|
- pgag_boost = 0x33;
|
|
|
- mixg_boost = 0x55;
|
|
|
- } else {
|
|
|
- bias = 0x25;
|
|
|
- cbias = 0x20;
|
|
|
- pag_boost = 0x4;
|
|
|
- pgag_boost = 0x03;
|
|
|
- mixg_boost = 0x65;
|
|
|
+ switch (field) {
|
|
|
+ case 0:
|
|
|
+ b43_phy_write(dev, reg, 0);
|
|
|
+ b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
|
|
|
+ break;
|
|
|
+ case 1:
|
|
|
+ if (!i) {
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
|
|
|
+ 0xFC3F, (value << 6));
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
|
|
|
+ 0xFFFE, 1);
|
|
|
+ b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
|
|
+ B43_NPHY_RFCTL_CMD_START);
|
|
|
+ for (j = 0; j < 100; j++) {
|
|
|
+ if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
|
|
|
+ j = 0;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ udelay(10);
|
|
|
}
|
|
|
- padg_boost = 0x77;
|
|
|
-
|
|
|
- b43_radio_write(dev,
|
|
|
- offset | B2056_TX_INTPAG_IMAIN_STAT,
|
|
|
- bias);
|
|
|
- b43_radio_write(dev,
|
|
|
- offset | B2056_TX_INTPAG_IAUX_STAT,
|
|
|
- bias);
|
|
|
- b43_radio_write(dev,
|
|
|
- offset | B2056_TX_INTPAG_CASCBIAS,
|
|
|
- cbias);
|
|
|
- b43_radio_write(dev,
|
|
|
- offset | B2056_TX_INTPAG_BOOST_TUNE,
|
|
|
- pag_boost);
|
|
|
- b43_radio_write(dev,
|
|
|
- offset | B2056_TX_PGAG_BOOST_TUNE,
|
|
|
- pgag_boost);
|
|
|
- b43_radio_write(dev,
|
|
|
- offset | B2056_TX_PADG_BOOST_TUNE,
|
|
|
- padg_boost);
|
|
|
- b43_radio_write(dev,
|
|
|
- offset | B2056_TX_MIXG_BOOST_TUNE,
|
|
|
- mixg_boost);
|
|
|
+ if (j)
|
|
|
+ b43err(dev->wl,
|
|
|
+ "intc override timeout\n");
|
|
|
+ b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
|
|
|
+ 0xFFFE);
|
|
|
} else {
|
|
|
- bias = dev->phy.is_40mhz ? 0x40 : 0x20;
|
|
|
- b43_radio_write(dev,
|
|
|
- offset | B2056_TX_INTPAG_IMAIN_STAT,
|
|
|
- bias);
|
|
|
- b43_radio_write(dev,
|
|
|
- offset | B2056_TX_INTPAG_IAUX_STAT,
|
|
|
- bias);
|
|
|
- b43_radio_write(dev,
|
|
|
- offset | B2056_TX_INTPAG_CASCBIAS,
|
|
|
- 0x30);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
|
|
|
+ 0xFC3F, (value << 6));
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
|
|
|
+ 0xFFFE, 1);
|
|
|
+ b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
|
|
+ B43_NPHY_RFCTL_CMD_RXTX);
|
|
|
+ for (j = 0; j < 100; j++) {
|
|
|
+ if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
|
|
|
+ j = 0;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ udelay(10);
|
|
|
+ }
|
|
|
+ if (j)
|
|
|
+ b43err(dev->wl,
|
|
|
+ "intc override timeout\n");
|
|
|
+ b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
|
|
|
+ 0xFFFE);
|
|
|
}
|
|
|
- b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
|
|
|
+ break;
|
|
|
+ case 2:
|
|
|
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
|
|
|
+ tmp = 0x0020;
|
|
|
+ val = value << 5;
|
|
|
+ } else {
|
|
|
+ tmp = 0x0010;
|
|
|
+ val = value << 4;
|
|
|
+ }
|
|
|
+ b43_phy_maskset(dev, reg, ~tmp, val);
|
|
|
+ break;
|
|
|
+ case 3:
|
|
|
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
|
|
|
+ tmp = 0x0001;
|
|
|
+ val = value;
|
|
|
+ } else {
|
|
|
+ tmp = 0x0004;
|
|
|
+ val = value << 2;
|
|
|
+ }
|
|
|
+ b43_phy_maskset(dev, reg, ~tmp, val);
|
|
|
+ break;
|
|
|
+ case 4:
|
|
|
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
|
|
|
+ tmp = 0x0002;
|
|
|
+ val = value << 1;
|
|
|
+ } else {
|
|
|
+ tmp = 0x0008;
|
|
|
+ val = value << 3;
|
|
|
+ }
|
|
|
+ b43_phy_maskset(dev, reg, ~tmp, val);
|
|
|
+ break;
|
|
|
}
|
|
|
- } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
|
|
|
- /* TODO */
|
|
|
}
|
|
|
+}
|
|
|
|
|
|
- udelay(50);
|
|
|
- /* VCO calibration */
|
|
|
- b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
|
|
|
- b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
|
|
|
- b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
|
|
|
- b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
|
|
|
- b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
|
|
|
- udelay(300);
|
|
|
+/**************************************************
|
|
|
+ * Various PHY ops
|
|
|
+ **************************************************/
|
|
|
+
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
|
|
|
+static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
|
|
|
+ const u16 *clip_st)
|
|
|
+{
|
|
|
+ b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
|
|
|
}
|
|
|
|
|
|
-static void b43_chantab_phy_upload(struct b43_wldev *dev,
|
|
|
- const struct b43_phy_n_sfo_cfg *e)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
|
|
|
+static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
|
|
|
{
|
|
|
- b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
|
|
|
- b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
|
|
|
- b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
|
|
|
- b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
|
|
|
- b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
|
|
|
- b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
|
|
|
+ clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
|
|
|
+ clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
|
|
|
-static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
|
|
|
+static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
|
|
|
{
|
|
|
- struct b43_phy_n *nphy = dev->phy.n;
|
|
|
- u8 i;
|
|
|
- u16 bmask, val, tmp;
|
|
|
- enum ieee80211_band band = b43_current_band(dev->wl);
|
|
|
+ u16 tmp;
|
|
|
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, 1);
|
|
|
+ if (dev->dev->core_rev == 16)
|
|
|
+ b43_mac_suspend(dev);
|
|
|
|
|
|
- nphy->txpwrctrl = enable;
|
|
|
- if (!enable) {
|
|
|
- if (dev->phy.rev >= 3 &&
|
|
|
- (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
|
|
|
- (B43_NPHY_TXPCTL_CMD_COEFF |
|
|
|
- B43_NPHY_TXPCTL_CMD_HWPCTLEN |
|
|
|
- B43_NPHY_TXPCTL_CMD_PCTLEN))) {
|
|
|
- /* We disable enabled TX pwr ctl, save it's state */
|
|
|
- nphy->tx_pwr_idx[0] = b43_phy_read(dev,
|
|
|
- B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
|
|
|
- nphy->tx_pwr_idx[1] = b43_phy_read(dev,
|
|
|
- B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
|
|
|
- }
|
|
|
+ tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
|
|
|
+ tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
|
|
|
+ B43_NPHY_CLASSCTL_WAITEDEN);
|
|
|
+ tmp &= ~mask;
|
|
|
+ tmp |= (val & mask);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
|
|
|
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
|
|
|
- for (i = 0; i < 84; i++)
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
|
|
|
+ if (dev->dev->core_rev == 16)
|
|
|
+ b43_mac_enable(dev);
|
|
|
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
|
|
|
- for (i = 0; i < 84; i++)
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
|
|
|
+ return tmp;
|
|
|
+}
|
|
|
|
|
|
- tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
|
|
|
- if (dev->phy.rev >= 3)
|
|
|
- tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
|
|
|
- b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
|
|
|
+static void b43_nphy_reset_cca(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ u16 bbcfg;
|
|
|
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
|
|
|
- b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
|
|
|
- } else {
|
|
|
- b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
|
|
|
- }
|
|
|
+ b43_phy_force_clock(dev, 1);
|
|
|
+ bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
|
|
|
+ b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
|
|
|
+ udelay(1);
|
|
|
+ b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
|
|
|
+ b43_phy_force_clock(dev, 0);
|
|
|
+ b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
|
|
|
+}
|
|
|
|
|
|
- if (dev->phy.rev == 2)
|
|
|
- b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
|
|
|
- ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
|
|
|
- else if (dev->phy.rev < 2)
|
|
|
- b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
|
|
|
- ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
|
|
|
+static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
|
|
|
+{
|
|
|
+ struct b43_phy *phy = &dev->phy;
|
|
|
+ struct b43_phy_n *nphy = phy->n;
|
|
|
|
|
|
- if (dev->phy.rev < 2 && dev->phy.is_40mhz)
|
|
|
- b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
|
|
|
+ if (enable) {
|
|
|
+ static const u16 clip[] = { 0xFFFF, 0xFFFF };
|
|
|
+ if (nphy->deaf_count++ == 0) {
|
|
|
+ nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
|
|
|
+ b43_nphy_classifier(dev, 0x7, 0);
|
|
|
+ b43_nphy_read_clip_detection(dev, nphy->clip_state);
|
|
|
+ b43_nphy_write_clip_detection(dev, clip);
|
|
|
+ }
|
|
|
+ b43_nphy_reset_cca(dev);
|
|
|
} else {
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
|
|
|
- nphy->adj_pwr_tbl);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
|
|
|
- nphy->adj_pwr_tbl);
|
|
|
-
|
|
|
- bmask = B43_NPHY_TXPCTL_CMD_COEFF |
|
|
|
- B43_NPHY_TXPCTL_CMD_HWPCTLEN;
|
|
|
- /* wl does useless check for "enable" param here */
|
|
|
- val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
|
|
|
- if (val)
|
|
|
- val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
|
|
|
- }
|
|
|
- b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
|
|
|
-
|
|
|
- if (band == IEEE80211_BAND_5GHZ) {
|
|
|
- b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
|
|
|
- ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
|
|
|
- if (dev->phy.rev > 1)
|
|
|
- b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
|
|
|
- ~B43_NPHY_TXPCTL_INIT_PIDXI1,
|
|
|
- 0x64);
|
|
|
- }
|
|
|
-
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- if (nphy->tx_pwr_idx[0] != 128 &&
|
|
|
- nphy->tx_pwr_idx[1] != 128) {
|
|
|
- /* Recover TX pwr ctl state */
|
|
|
- b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
|
|
|
- ~B43_NPHY_TXPCTL_CMD_INIT,
|
|
|
- nphy->tx_pwr_idx[0]);
|
|
|
- if (dev->phy.rev > 1)
|
|
|
- b43_phy_maskset(dev,
|
|
|
- B43_NPHY_TXPCTL_INIT,
|
|
|
- ~0xff, nphy->tx_pwr_idx[1]);
|
|
|
- }
|
|
|
- }
|
|
|
-
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
|
|
|
- b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
|
|
|
- } else {
|
|
|
- b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
|
|
|
- }
|
|
|
-
|
|
|
- if (dev->phy.rev == 2)
|
|
|
- b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
|
|
|
- else if (dev->phy.rev < 2)
|
|
|
- b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
|
|
|
-
|
|
|
- if (dev->phy.rev < 2 && dev->phy.is_40mhz)
|
|
|
- b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
|
|
|
-
|
|
|
- if (b43_nphy_ipa(dev)) {
|
|
|
- b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
|
|
|
- b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
|
|
|
+ if (--nphy->deaf_count == 0) {
|
|
|
+ b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
|
|
|
+ b43_nphy_write_clip_detection(dev, nphy->clip_state);
|
|
|
}
|
|
|
}
|
|
|
-
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, 0);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
|
|
|
-static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
|
|
|
+static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
|
|
|
{
|
|
|
struct b43_phy_n *nphy = dev->phy.n;
|
|
|
- struct ssb_sprom *sprom = dev->dev->bus_sprom;
|
|
|
|
|
|
- u8 txpi[2], bbmult, i;
|
|
|
- u16 tmp, radio_gain, dac_gain;
|
|
|
- u16 freq = dev->phy.channel_freq;
|
|
|
- u32 txgain;
|
|
|
- /* u32 gaintbl; rev3+ */
|
|
|
+ u8 i;
|
|
|
+ s16 tmp;
|
|
|
+ u16 data[4];
|
|
|
+ s16 gain[2];
|
|
|
+ u16 minmax[2];
|
|
|
+ static const u16 lna_gain[4] = { -2, 10, 19, 25 };
|
|
|
|
|
|
if (nphy->hang_avoid)
|
|
|
b43_nphy_stay_in_carrier_search(dev, 1);
|
|
|
|
|
|
- if (dev->phy.rev >= 7) {
|
|
|
- txpi[0] = txpi[1] = 30;
|
|
|
- } else if (dev->phy.rev >= 3) {
|
|
|
- txpi[0] = 40;
|
|
|
- txpi[1] = 40;
|
|
|
- } else if (sprom->revision < 4) {
|
|
|
- txpi[0] = 72;
|
|
|
- txpi[1] = 72;
|
|
|
- } else {
|
|
|
+ if (nphy->gain_boost) {
|
|
|
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
|
|
|
- txpi[0] = sprom->txpid2g[0];
|
|
|
- txpi[1] = sprom->txpid2g[1];
|
|
|
- } else if (freq >= 4900 && freq < 5100) {
|
|
|
- txpi[0] = sprom->txpid5gl[0];
|
|
|
- txpi[1] = sprom->txpid5gl[1];
|
|
|
- } else if (freq >= 5100 && freq < 5500) {
|
|
|
- txpi[0] = sprom->txpid5g[0];
|
|
|
- txpi[1] = sprom->txpid5g[1];
|
|
|
- } else if (freq >= 5500) {
|
|
|
- txpi[0] = sprom->txpid5gh[0];
|
|
|
- txpi[1] = sprom->txpid5gh[1];
|
|
|
+ gain[0] = 6;
|
|
|
+ gain[1] = 6;
|
|
|
} else {
|
|
|
- txpi[0] = 91;
|
|
|
- txpi[1] = 91;
|
|
|
+ tmp = 40370 - 315 * dev->phy.channel;
|
|
|
+ gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
|
|
|
+ tmp = 23242 - 224 * dev->phy.channel;
|
|
|
+ gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
|
|
|
}
|
|
|
+ } else {
|
|
|
+ gain[0] = 0;
|
|
|
+ gain[1] = 0;
|
|
|
}
|
|
|
- if (dev->phy.rev < 7 &&
|
|
|
- (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 10))
|
|
|
- txpi[0] = txpi[1] = 91;
|
|
|
-
|
|
|
- /*
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- nphy->txpwrindex[i].index_internal = txpi[i];
|
|
|
- nphy->txpwrindex[i].index_internal_save = txpi[i];
|
|
|
- }
|
|
|
- */
|
|
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- if (b43_nphy_ipa(dev)) {
|
|
|
- txgain = *(b43_nphy_get_ipa_gain_table(dev) +
|
|
|
- txpi[i]);
|
|
|
- } else if (b43_current_band(dev->wl) ==
|
|
|
- IEEE80211_BAND_5GHZ) {
|
|
|
- /* FIXME: use 5GHz tables */
|
|
|
- txgain =
|
|
|
- b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
|
|
|
- } else {
|
|
|
- if (dev->phy.rev >= 5 &&
|
|
|
- sprom->fem.ghz5.extpa_gain == 3)
|
|
|
- ; /* FIXME: 5GHz_txgain_HiPwrEPA */
|
|
|
- txgain =
|
|
|
- b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
|
|
|
- }
|
|
|
- radio_gain = (txgain >> 16) & 0x1FFFF;
|
|
|
- } else {
|
|
|
- txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
|
|
|
- radio_gain = (txgain >> 16) & 0x1FFF;
|
|
|
- }
|
|
|
-
|
|
|
- if (dev->phy.rev >= 7)
|
|
|
- dac_gain = (txgain >> 8) & 0x7;
|
|
|
- else
|
|
|
- dac_gain = (txgain >> 8) & 0x3F;
|
|
|
- bbmult = txgain & 0xFF;
|
|
|
-
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- if (i == 0)
|
|
|
- b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
|
|
|
- else
|
|
|
- b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
|
|
|
+ if (nphy->elna_gain_config) {
|
|
|
+ data[0] = 19 + gain[i];
|
|
|
+ data[1] = 25 + gain[i];
|
|
|
+ data[2] = 25 + gain[i];
|
|
|
+ data[3] = 25 + gain[i];
|
|
|
} else {
|
|
|
- b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
|
|
|
+ data[0] = lna_gain[0] + gain[i];
|
|
|
+ data[1] = lna_gain[1] + gain[i];
|
|
|
+ data[2] = lna_gain[2] + gain[i];
|
|
|
+ data[3] = lna_gain[3] + gain[i];
|
|
|
}
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
|
|
|
|
|
|
- if (i == 0)
|
|
|
- b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
|
|
|
- else
|
|
|
- b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
|
|
|
-
|
|
|
- b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
|
|
|
-
|
|
|
- tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
|
|
|
- if (i == 0)
|
|
|
- tmp = (tmp & 0x00FF) | (bbmult << 8);
|
|
|
- else
|
|
|
- tmp = (tmp & 0xFF00) | bbmult;
|
|
|
- b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
|
|
|
-
|
|
|
- if (b43_nphy_ipa(dev)) {
|
|
|
- u32 tmp32;
|
|
|
- u16 reg = (i == 0) ?
|
|
|
- B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
|
|
|
- tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
|
|
|
- 576 + txpi[i]));
|
|
|
- b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
|
|
|
- b43_phy_set(dev, reg, 0x4);
|
|
|
- }
|
|
|
+ minmax[i] = 23 + gain[i];
|
|
|
}
|
|
|
|
|
|
- b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
|
|
|
+ minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
|
|
|
+ minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
|
|
|
|
|
|
if (nphy->hang_avoid)
|
|
|
b43_nphy_stay_in_carrier_search(dev, 0);
|
|
|
}
|
|
|
|
|
|
-static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
|
|
|
+static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
|
|
|
+ u8 *events, u8 *delays, u8 length)
|
|
|
{
|
|
|
- struct b43_phy *phy = &dev->phy;
|
|
|
-
|
|
|
- const u32 *table = NULL;
|
|
|
-#if 0
|
|
|
- TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
|
|
|
- u32 rfpwr_offset;
|
|
|
- u8 pga_gain;
|
|
|
- int i;
|
|
|
-#endif
|
|
|
+ struct b43_phy_n *nphy = dev->phy.n;
|
|
|
+ u8 i;
|
|
|
+ u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
|
|
|
+ u16 offset1 = cmd << 4;
|
|
|
+ u16 offset2 = offset1 + 0x80;
|
|
|
|
|
|
- if (phy->rev >= 3) {
|
|
|
- if (b43_nphy_ipa(dev)) {
|
|
|
- table = b43_nphy_get_ipa_gain_table(dev);
|
|
|
- } else {
|
|
|
- if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
|
|
|
- if (phy->rev == 3)
|
|
|
- table = b43_ntab_tx_gain_rev3_5ghz;
|
|
|
- if (phy->rev == 4)
|
|
|
- table = b43_ntab_tx_gain_rev4_5ghz;
|
|
|
- else
|
|
|
- table = b43_ntab_tx_gain_rev5plus_5ghz;
|
|
|
- } else {
|
|
|
- table = b43_ntab_tx_gain_rev3plus_2ghz;
|
|
|
- }
|
|
|
- }
|
|
|
- } else {
|
|
|
- table = b43_ntab_tx_gain_rev0_1_2;
|
|
|
- }
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, true);
|
|
|
|
|
|
- if (phy->rev >= 3) {
|
|
|
-#if 0
|
|
|
- nphy->gmval = (table[0] >> 16) & 0x7000;
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
|
|
|
|
|
|
- for (i = 0; i < 128; i++) {
|
|
|
- pga_gain = (table[i] >> 24) & 0xF;
|
|
|
- if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
|
|
|
- rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
|
|
|
- else
|
|
|
- rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
|
|
|
- b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
|
|
|
- rfpwr_offset);
|
|
|
- b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
|
|
|
- rfpwr_offset);
|
|
|
- }
|
|
|
-#endif
|
|
|
+ for (i = length; i < 16; i++) {
|
|
|
+ b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
|
|
|
+ b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
|
|
|
}
|
|
|
+
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, false);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
|
|
|
-static void b43_radio_2055_setup(struct b43_wldev *dev,
|
|
|
- const struct b43_nphy_channeltab_entry_rev2 *e)
|
|
|
-{
|
|
|
- B43_WARN_ON(dev->phy.rev >= 3);
|
|
|
-
|
|
|
- b43_chantab_radio_upload(dev, e);
|
|
|
- udelay(50);
|
|
|
- b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
|
|
|
- b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
|
|
|
- b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
|
|
|
- b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
|
|
|
- udelay(300);
|
|
|
-}
|
|
|
+/**************************************************
|
|
|
+ * Radio 0x2056
|
|
|
+ **************************************************/
|
|
|
|
|
|
-static void b43_radio_init2055_pre(struct b43_wldev *dev)
|
|
|
+static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
|
|
|
+ const struct b43_nphy_channeltab_entry_rev3 *e)
|
|
|
{
|
|
|
- b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
|
|
|
- ~B43_NPHY_RFCTL_CMD_PORFORCE);
|
|
|
- b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
|
|
- B43_NPHY_RFCTL_CMD_CHIP0PU |
|
|
|
- B43_NPHY_RFCTL_CMD_OEPORFORCE);
|
|
|
- b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
|
|
- B43_NPHY_RFCTL_CMD_PORFORCE);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
|
|
|
+ e->radio_syn_pll_loopfilter1);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
|
|
|
+ e->radio_syn_pll_loopfilter2);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
|
|
|
+ e->radio_syn_pll_loopfilter3);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
|
|
|
+ e->radio_syn_pll_loopfilter4);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
|
|
|
+ e->radio_syn_pll_loopfilter5);
|
|
|
+ b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
|
|
|
+ e->radio_syn_reserved_addr27);
|
|
|
+ b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
|
|
|
+ e->radio_syn_reserved_addr28);
|
|
|
+ b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
|
|
|
+ e->radio_syn_reserved_addr29);
|
|
|
+ b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
|
|
|
+ e->radio_syn_logen_vcobuf1);
|
|
|
+ b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
|
|
|
+ b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
|
|
|
+ b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
|
|
|
+
|
|
|
+ b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
|
|
|
+ e->radio_rx0_lnaa_tune);
|
|
|
+ b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
|
|
|
+ e->radio_rx0_lnag_tune);
|
|
|
+
|
|
|
+ b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
|
|
|
+ e->radio_tx0_intpaa_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
|
|
|
+ e->radio_tx0_intpag_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
|
|
|
+ e->radio_tx0_pada_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
|
|
|
+ e->radio_tx0_padg_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
|
|
|
+ e->radio_tx0_pgaa_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
|
|
|
+ e->radio_tx0_pgag_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
|
|
|
+ e->radio_tx0_mixa_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
|
|
|
+ e->radio_tx0_mixg_boost_tune);
|
|
|
+
|
|
|
+ b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
|
|
|
+ e->radio_rx1_lnaa_tune);
|
|
|
+ b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
|
|
|
+ e->radio_rx1_lnag_tune);
|
|
|
+
|
|
|
+ b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
|
|
|
+ e->radio_tx1_intpaa_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
|
|
|
+ e->radio_tx1_intpag_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
|
|
|
+ e->radio_tx1_pada_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
|
|
|
+ e->radio_tx1_padg_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
|
|
|
+ e->radio_tx1_pgaa_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
|
|
|
+ e->radio_tx1_pgag_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
|
|
|
+ e->radio_tx1_mixa_boost_tune);
|
|
|
+ b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
|
|
|
+ e->radio_tx1_mixg_boost_tune);
|
|
|
}
|
|
|
|
|
|
-static void b43_radio_init2055_post(struct b43_wldev *dev)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
|
|
|
+static void b43_radio_2056_setup(struct b43_wldev *dev,
|
|
|
+ const struct b43_nphy_channeltab_entry_rev3 *e)
|
|
|
{
|
|
|
- struct b43_phy_n *nphy = dev->phy.n;
|
|
|
struct ssb_sprom *sprom = dev->dev->bus_sprom;
|
|
|
- int i;
|
|
|
- u16 val;
|
|
|
- bool workaround = false;
|
|
|
+ enum ieee80211_band band = b43_current_band(dev->wl);
|
|
|
+ u16 offset;
|
|
|
+ u8 i;
|
|
|
+ u16 bias, cbias, pag_boost, pgag_boost, mixg_boost, padg_boost;
|
|
|
|
|
|
- if (sprom->revision < 4)
|
|
|
- workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
|
|
|
- && dev->dev->board_type == 0x46D
|
|
|
- && dev->dev->board_rev >= 0x41);
|
|
|
- else
|
|
|
- workaround =
|
|
|
- !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
|
|
|
+ B43_WARN_ON(dev->phy.rev < 3);
|
|
|
|
|
|
- b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
|
|
|
- if (workaround) {
|
|
|
- b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
|
|
|
- b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
|
|
|
- }
|
|
|
- b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
|
|
|
- b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
|
|
|
- b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
|
|
|
- b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
|
|
|
- b43_radio_set(dev, B2055_CAL_MISC, 0x1);
|
|
|
- msleep(1);
|
|
|
- b43_radio_set(dev, B2055_CAL_MISC, 0x40);
|
|
|
- for (i = 0; i < 200; i++) {
|
|
|
- val = b43_radio_read(dev, B2055_CAL_COUT2);
|
|
|
- if (val & 0x80) {
|
|
|
- i = 0;
|
|
|
- break;
|
|
|
+ b43_chantab_radio_2056_upload(dev, e);
|
|
|
+ b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
|
|
|
+
|
|
|
+ if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
|
|
|
+ b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
|
|
|
+ if (dev->dev->chip_id == 0x4716) {
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
|
|
|
+ } else {
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
|
|
|
}
|
|
|
- udelay(10);
|
|
|
}
|
|
|
- if (i)
|
|
|
- b43err(dev->wl, "radio post init timeout\n");
|
|
|
- b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
|
|
|
- b43_switch_channel(dev, dev->phy.channel);
|
|
|
- b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
|
|
|
- b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
|
|
|
- b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
|
|
|
- b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
|
|
|
- b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
|
|
|
- b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
|
|
|
- if (!nphy->gain_boost) {
|
|
|
- b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
|
|
|
- b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
|
|
|
- } else {
|
|
|
- b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
|
|
|
- b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
|
|
|
+ if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
|
|
|
+ b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
|
|
|
}
|
|
|
- udelay(2);
|
|
|
-}
|
|
|
|
|
|
-/*
|
|
|
- * Initialize a Broadcom 2055 N-radio
|
|
|
- * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
|
|
|
- */
|
|
|
-static void b43_radio_init2055(struct b43_wldev *dev)
|
|
|
-{
|
|
|
- b43_radio_init2055_pre(dev);
|
|
|
- if (b43_status(dev) < B43_STAT_INITIALIZED) {
|
|
|
- /* Follow wl, not specs. Do not force uploading all regs */
|
|
|
- b2055_upload_inittab(dev, 0, 0);
|
|
|
- } else {
|
|
|
- bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
|
|
|
- b2055_upload_inittab(dev, ghz5, 0);
|
|
|
+ if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
|
|
|
+ for (i = 0; i < 2; i++) {
|
|
|
+ offset = i ? B2056_TX1 : B2056_TX0;
|
|
|
+ if (dev->phy.rev >= 5) {
|
|
|
+ b43_radio_write(dev,
|
|
|
+ offset | B2056_TX_PADG_IDAC, 0xcc);
|
|
|
+
|
|
|
+ if (dev->dev->chip_id == 0x4716) {
|
|
|
+ bias = 0x40;
|
|
|
+ cbias = 0x45;
|
|
|
+ pag_boost = 0x5;
|
|
|
+ pgag_boost = 0x33;
|
|
|
+ mixg_boost = 0x55;
|
|
|
+ } else {
|
|
|
+ bias = 0x25;
|
|
|
+ cbias = 0x20;
|
|
|
+ pag_boost = 0x4;
|
|
|
+ pgag_boost = 0x03;
|
|
|
+ mixg_boost = 0x65;
|
|
|
+ }
|
|
|
+ padg_boost = 0x77;
|
|
|
+
|
|
|
+ b43_radio_write(dev,
|
|
|
+ offset | B2056_TX_INTPAG_IMAIN_STAT,
|
|
|
+ bias);
|
|
|
+ b43_radio_write(dev,
|
|
|
+ offset | B2056_TX_INTPAG_IAUX_STAT,
|
|
|
+ bias);
|
|
|
+ b43_radio_write(dev,
|
|
|
+ offset | B2056_TX_INTPAG_CASCBIAS,
|
|
|
+ cbias);
|
|
|
+ b43_radio_write(dev,
|
|
|
+ offset | B2056_TX_INTPAG_BOOST_TUNE,
|
|
|
+ pag_boost);
|
|
|
+ b43_radio_write(dev,
|
|
|
+ offset | B2056_TX_PGAG_BOOST_TUNE,
|
|
|
+ pgag_boost);
|
|
|
+ b43_radio_write(dev,
|
|
|
+ offset | B2056_TX_PADG_BOOST_TUNE,
|
|
|
+ padg_boost);
|
|
|
+ b43_radio_write(dev,
|
|
|
+ offset | B2056_TX_MIXG_BOOST_TUNE,
|
|
|
+ mixg_boost);
|
|
|
+ } else {
|
|
|
+ bias = dev->phy.is_40mhz ? 0x40 : 0x20;
|
|
|
+ b43_radio_write(dev,
|
|
|
+ offset | B2056_TX_INTPAG_IMAIN_STAT,
|
|
|
+ bias);
|
|
|
+ b43_radio_write(dev,
|
|
|
+ offset | B2056_TX_INTPAG_IAUX_STAT,
|
|
|
+ bias);
|
|
|
+ b43_radio_write(dev,
|
|
|
+ offset | B2056_TX_INTPAG_CASCBIAS,
|
|
|
+ 0x30);
|
|
|
+ }
|
|
|
+ b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
|
|
|
+ }
|
|
|
+ } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
|
|
|
+ /* TODO */
|
|
|
}
|
|
|
- b43_radio_init2055_post(dev);
|
|
|
+
|
|
|
+ udelay(50);
|
|
|
+ /* VCO calibration */
|
|
|
+ b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
|
|
|
+ b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
|
|
|
+ b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
|
|
|
+ b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
|
|
|
+ b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
|
|
|
+ udelay(300);
|
|
|
}
|
|
|
|
|
|
static void b43_radio_init2056_pre(struct b43_wldev *dev)
|
|
@@ -771,830 +693,1013 @@ static void b43_radio_init2056(struct b43_wldev *dev)
|
|
|
b43_radio_init2056_post(dev);
|
|
|
}
|
|
|
|
|
|
-/*
|
|
|
- * Upload the N-PHY tables.
|
|
|
- * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
|
|
|
- */
|
|
|
-static void b43_nphy_tables_init(struct b43_wldev *dev)
|
|
|
+/**************************************************
|
|
|
+ * Radio 0x2055
|
|
|
+ **************************************************/
|
|
|
+
|
|
|
+static void b43_chantab_radio_upload(struct b43_wldev *dev,
|
|
|
+ const struct b43_nphy_channeltab_entry_rev2 *e)
|
|
|
{
|
|
|
- if (dev->phy.rev < 3)
|
|
|
- b43_nphy_rev0_1_2_tables_init(dev);
|
|
|
- else
|
|
|
- b43_nphy_rev3plus_tables_init(dev);
|
|
|
-}
|
|
|
+ b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
|
|
|
+ b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
|
|
|
+ b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
|
|
|
+ b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
|
|
|
+ b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
|
|
|
-static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
|
|
|
-{
|
|
|
- struct b43_phy_n *nphy = dev->phy.n;
|
|
|
- enum ieee80211_band band;
|
|
|
- u16 tmp;
|
|
|
+ b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
|
|
|
+ b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
|
|
|
+ b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
|
|
|
+ b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
|
|
|
+ b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
|
|
|
|
|
|
- if (!enable) {
|
|
|
- nphy->rfctrl_intc1_save = b43_phy_read(dev,
|
|
|
- B43_NPHY_RFCTL_INTC1);
|
|
|
- nphy->rfctrl_intc2_save = b43_phy_read(dev,
|
|
|
- B43_NPHY_RFCTL_INTC2);
|
|
|
- band = b43_current_band(dev->wl);
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- if (band == IEEE80211_BAND_5GHZ)
|
|
|
- tmp = 0x600;
|
|
|
- else
|
|
|
- tmp = 0x480;
|
|
|
- } else {
|
|
|
- if (band == IEEE80211_BAND_5GHZ)
|
|
|
- tmp = 0x180;
|
|
|
- else
|
|
|
- tmp = 0x120;
|
|
|
- }
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
|
|
|
- } else {
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
|
|
|
- nphy->rfctrl_intc1_save);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
|
|
|
- nphy->rfctrl_intc2_save);
|
|
|
- }
|
|
|
-}
|
|
|
+ b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
|
|
|
+ b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
|
|
|
+ b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
|
|
|
+ b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
|
|
|
+ b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
|
|
|
-static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
|
|
|
-{
|
|
|
- u16 tmp;
|
|
|
+ b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
|
|
|
+ b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
|
|
|
+ b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
|
|
|
+ b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
|
|
|
+ b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
|
|
|
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- if (b43_nphy_ipa(dev)) {
|
|
|
- tmp = 4;
|
|
|
- b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
|
|
|
- (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
|
|
|
- }
|
|
|
+ b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
|
|
|
+ b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
|
|
|
+ b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
|
|
|
+ b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
|
|
|
+ b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
|
|
|
|
|
|
- tmp = 1;
|
|
|
- b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
|
|
|
- (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
|
|
|
- }
|
|
|
+ b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
|
|
|
+ b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
|
|
|
-static void b43_nphy_reset_cca(struct b43_wldev *dev)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
|
|
|
+static void b43_radio_2055_setup(struct b43_wldev *dev,
|
|
|
+ const struct b43_nphy_channeltab_entry_rev2 *e)
|
|
|
{
|
|
|
- u16 bbcfg;
|
|
|
+ B43_WARN_ON(dev->phy.rev >= 3);
|
|
|
|
|
|
- b43_phy_force_clock(dev, 1);
|
|
|
- bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
|
|
|
- b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
|
|
|
- udelay(1);
|
|
|
- b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
|
|
|
- b43_phy_force_clock(dev, 0);
|
|
|
- b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
|
|
|
+ b43_chantab_radio_upload(dev, e);
|
|
|
+ udelay(50);
|
|
|
+ b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
|
|
|
+ b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
|
|
|
+ b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
|
|
|
+ b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
|
|
|
+ udelay(300);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
|
|
|
-static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
|
|
|
+static void b43_radio_init2055_pre(struct b43_wldev *dev)
|
|
|
{
|
|
|
- u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
|
|
|
-
|
|
|
- mimocfg |= B43_NPHY_MIMOCFG_AUTO;
|
|
|
- if (preamble == 1)
|
|
|
- mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
|
|
|
- else
|
|
|
- mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
|
|
|
-
|
|
|
- b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
|
|
|
+ ~B43_NPHY_RFCTL_CMD_PORFORCE);
|
|
|
+ b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
|
|
+ B43_NPHY_RFCTL_CMD_CHIP0PU |
|
|
|
+ B43_NPHY_RFCTL_CMD_OEPORFORCE);
|
|
|
+ b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
|
|
+ B43_NPHY_RFCTL_CMD_PORFORCE);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
|
|
|
-static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
|
|
|
+static void b43_radio_init2055_post(struct b43_wldev *dev)
|
|
|
{
|
|
|
struct b43_phy_n *nphy = dev->phy.n;
|
|
|
-
|
|
|
- bool override = false;
|
|
|
- u16 chain = 0x33;
|
|
|
-
|
|
|
- if (nphy->txrx_chain == 0) {
|
|
|
- chain = 0x11;
|
|
|
- override = true;
|
|
|
- } else if (nphy->txrx_chain == 1) {
|
|
|
- chain = 0x22;
|
|
|
- override = true;
|
|
|
- }
|
|
|
-
|
|
|
- b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
|
|
|
- ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
|
|
|
- chain);
|
|
|
-
|
|
|
- if (override)
|
|
|
- b43_phy_set(dev, B43_NPHY_RFSEQMODE,
|
|
|
- B43_NPHY_RFSEQMODE_CAOVER);
|
|
|
- else
|
|
|
- b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
|
|
|
- ~B43_NPHY_RFSEQMODE_CAOVER);
|
|
|
-}
|
|
|
-
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
|
|
|
-static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
|
|
|
- u16 samps, u8 time, bool wait)
|
|
|
-{
|
|
|
+ struct ssb_sprom *sprom = dev->dev->bus_sprom;
|
|
|
int i;
|
|
|
- u16 tmp;
|
|
|
+ u16 val;
|
|
|
+ bool workaround = false;
|
|
|
|
|
|
- b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
|
|
|
- if (wait)
|
|
|
- b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
|
|
|
+ if (sprom->revision < 4)
|
|
|
+ workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
|
|
|
+ && dev->dev->board_type == 0x46D
|
|
|
+ && dev->dev->board_rev >= 0x41);
|
|
|
else
|
|
|
- b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
|
|
|
-
|
|
|
- b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
|
|
|
-
|
|
|
- for (i = 1000; i; i--) {
|
|
|
- tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
|
|
|
- if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
|
|
|
- est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
|
|
|
- b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
|
|
|
- est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
|
|
|
- b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
|
|
|
- est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
|
|
|
- b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
|
|
|
+ workaround =
|
|
|
+ !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
|
|
|
|
|
|
- est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
|
|
|
- b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
|
|
|
- est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
|
|
|
- b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
|
|
|
- est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
|
|
|
- b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
|
|
|
- return;
|
|
|
+ b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
|
|
|
+ if (workaround) {
|
|
|
+ b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
|
|
|
+ b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
|
|
|
+ }
|
|
|
+ b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
|
|
|
+ b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
|
|
|
+ b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
|
|
|
+ b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
|
|
|
+ b43_radio_set(dev, B2055_CAL_MISC, 0x1);
|
|
|
+ msleep(1);
|
|
|
+ b43_radio_set(dev, B2055_CAL_MISC, 0x40);
|
|
|
+ for (i = 0; i < 200; i++) {
|
|
|
+ val = b43_radio_read(dev, B2055_CAL_COUT2);
|
|
|
+ if (val & 0x80) {
|
|
|
+ i = 0;
|
|
|
+ break;
|
|
|
}
|
|
|
udelay(10);
|
|
|
}
|
|
|
- memset(est, 0, sizeof(*est));
|
|
|
+ if (i)
|
|
|
+ b43err(dev->wl, "radio post init timeout\n");
|
|
|
+ b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
|
|
|
+ b43_switch_channel(dev, dev->phy.channel);
|
|
|
+ b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
|
|
|
+ b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
|
|
|
+ b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
|
|
|
+ b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
|
|
|
+ b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
|
|
|
+ b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
|
|
|
+ if (!nphy->gain_boost) {
|
|
|
+ b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
|
|
|
+ b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
|
|
|
+ } else {
|
|
|
+ b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
|
|
|
+ b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
|
|
|
+ }
|
|
|
+ udelay(2);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
|
|
|
-static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
|
|
|
- struct b43_phy_n_iq_comp *pcomp)
|
|
|
+/*
|
|
|
+ * Initialize a Broadcom 2055 N-radio
|
|
|
+ * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
|
|
|
+ */
|
|
|
+static void b43_radio_init2055(struct b43_wldev *dev)
|
|
|
{
|
|
|
- if (write) {
|
|
|
- b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
|
|
|
- b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
|
|
|
- b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
|
|
|
- b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
|
|
|
+ b43_radio_init2055_pre(dev);
|
|
|
+ if (b43_status(dev) < B43_STAT_INITIALIZED) {
|
|
|
+ /* Follow wl, not specs. Do not force uploading all regs */
|
|
|
+ b2055_upload_inittab(dev, 0, 0);
|
|
|
} else {
|
|
|
- pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
|
|
|
- pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
|
|
|
- pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
|
|
|
- pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
|
|
|
+ bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
|
|
|
+ b2055_upload_inittab(dev, ghz5, 0);
|
|
|
}
|
|
|
+ b43_radio_init2055_post(dev);
|
|
|
}
|
|
|
|
|
|
-#if 0
|
|
|
-/* Ready but not used anywhere */
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
|
|
|
-static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
|
|
|
-{
|
|
|
- u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
|
|
|
+/**************************************************
|
|
|
+ * Samples
|
|
|
+ **************************************************/
|
|
|
|
|
|
- b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
|
|
|
- if (core == 0) {
|
|
|
- b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
|
|
|
- b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
|
|
|
- } else {
|
|
|
- b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
|
|
|
- b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
|
|
|
- }
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
|
|
|
- b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
|
|
|
- b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
|
|
|
- b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
|
|
|
+static int b43_nphy_load_samples(struct b43_wldev *dev,
|
|
|
+ struct b43_c32 *samples, u16 len) {
|
|
|
+ struct b43_phy_n *nphy = dev->phy.n;
|
|
|
+ u16 i;
|
|
|
+ u32 *data;
|
|
|
+
|
|
|
+ data = kzalloc(len * sizeof(u32), GFP_KERNEL);
|
|
|
+ if (!data) {
|
|
|
+ b43err(dev->wl, "allocation for samples loading failed\n");
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, 1);
|
|
|
+
|
|
|
+ for (i = 0; i < len; i++) {
|
|
|
+ data[i] = (samples[i].i & 0x3FF << 10);
|
|
|
+ data[i] |= samples[i].q & 0x3FF;
|
|
|
+ }
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
|
|
|
+
|
|
|
+ kfree(data);
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, 0);
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
|
|
|
-static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
|
|
|
+static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
|
|
|
+ bool test)
|
|
|
{
|
|
|
- u8 rxval, txval;
|
|
|
- u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
|
|
|
+ int i;
|
|
|
+ u16 bw, len, rot, angle;
|
|
|
+ struct b43_c32 *samples;
|
|
|
|
|
|
- regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
|
|
|
- if (core == 0) {
|
|
|
- regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
|
|
|
- regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
|
|
|
- } else {
|
|
|
- regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
|
|
|
- regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
|
|
|
- }
|
|
|
- regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
|
|
|
- regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
|
|
|
- regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
|
|
|
- regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
|
|
|
- regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
|
|
|
- regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
|
|
|
- regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
|
|
|
- regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
|
|
|
|
|
|
- b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
|
|
|
- b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
|
|
|
+ bw = (dev->phy.is_40mhz) ? 40 : 20;
|
|
|
+ len = bw << 3;
|
|
|
|
|
|
- b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
|
|
|
- ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
|
|
|
- ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
|
|
|
- b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
|
|
|
- ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
|
|
|
- b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
|
|
|
- (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
|
|
|
- b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
|
|
|
- (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
|
|
|
+ if (test) {
|
|
|
+ if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
|
|
|
+ bw = 82;
|
|
|
+ else
|
|
|
+ bw = 80;
|
|
|
|
|
|
- if (core == 0) {
|
|
|
- b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
|
|
|
- b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
|
|
|
- } else {
|
|
|
- b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
|
|
|
- b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
|
|
|
+ if (dev->phy.is_40mhz)
|
|
|
+ bw <<= 1;
|
|
|
+
|
|
|
+ len = bw << 1;
|
|
|
}
|
|
|
|
|
|
- b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
|
|
|
- b43_nphy_rf_control_override(dev, 8, 0, 3, false);
|
|
|
- b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
|
|
|
+ samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
|
|
|
+ if (!samples) {
|
|
|
+ b43err(dev->wl, "allocation for samples generation failed\n");
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+ rot = (((freq * 36) / bw) << 16) / 100;
|
|
|
+ angle = 0;
|
|
|
|
|
|
- if (core == 0) {
|
|
|
- rxval = 1;
|
|
|
- txval = 8;
|
|
|
- } else {
|
|
|
- rxval = 4;
|
|
|
- txval = 2;
|
|
|
+ for (i = 0; i < len; i++) {
|
|
|
+ samples[i] = b43_cordic(angle);
|
|
|
+ angle += rot;
|
|
|
+ samples[i].q = CORDIC_CONVERT(samples[i].q * max);
|
|
|
+ samples[i].i = CORDIC_CONVERT(samples[i].i * max);
|
|
|
}
|
|
|
- b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
|
|
|
- b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
|
|
|
+
|
|
|
+ i = b43_nphy_load_samples(dev, samples, len);
|
|
|
+ kfree(samples);
|
|
|
+ return (i < 0) ? 0 : len;
|
|
|
}
|
|
|
-#endif
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
|
|
|
-static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
|
|
|
+static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
|
|
|
+ u16 wait, bool iqmode, bool dac_test)
|
|
|
{
|
|
|
+ struct b43_phy_n *nphy = dev->phy.n;
|
|
|
int i;
|
|
|
- s32 iq;
|
|
|
- u32 ii;
|
|
|
- u32 qq;
|
|
|
- int iq_nbits, qq_nbits;
|
|
|
- int arsh, brsh;
|
|
|
- u16 tmp, a, b;
|
|
|
+ u16 seq_mode;
|
|
|
+ u32 tmp;
|
|
|
|
|
|
- struct nphy_iq_est est;
|
|
|
- struct b43_phy_n_iq_comp old;
|
|
|
- struct b43_phy_n_iq_comp new = { };
|
|
|
- bool error = false;
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, true);
|
|
|
|
|
|
- if (mask == 0)
|
|
|
- return;
|
|
|
+ if ((nphy->bb_mult_save & 0x80000000) == 0) {
|
|
|
+ tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
|
|
|
+ nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
|
|
|
+ }
|
|
|
|
|
|
- b43_nphy_rx_iq_coeffs(dev, false, &old);
|
|
|
- b43_nphy_rx_iq_coeffs(dev, true, &new);
|
|
|
- b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
|
|
|
- new = old;
|
|
|
+ if (!dev->phy.is_40mhz)
|
|
|
+ tmp = 0x6464;
|
|
|
+ else
|
|
|
+ tmp = 0x4747;
|
|
|
+ b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
|
|
|
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- if (i == 0 && (mask & 1)) {
|
|
|
- iq = est.iq0_prod;
|
|
|
- ii = est.i0_pwr;
|
|
|
- qq = est.q0_pwr;
|
|
|
- } else if (i == 1 && (mask & 2)) {
|
|
|
- iq = est.iq1_prod;
|
|
|
- ii = est.i1_pwr;
|
|
|
- qq = est.q1_pwr;
|
|
|
- } else {
|
|
|
- continue;
|
|
|
- }
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, false);
|
|
|
|
|
|
- if (ii + qq < 2) {
|
|
|
- error = true;
|
|
|
- break;
|
|
|
- }
|
|
|
+ b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
|
|
|
|
|
|
- iq_nbits = fls(abs(iq));
|
|
|
- qq_nbits = fls(qq);
|
|
|
+ if (loops != 0xFFFF)
|
|
|
+ b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
|
|
|
+ else
|
|
|
+ b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
|
|
|
|
|
|
- arsh = iq_nbits - 20;
|
|
|
- if (arsh >= 0) {
|
|
|
- a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
|
|
|
- tmp = ii >> arsh;
|
|
|
- } else {
|
|
|
- a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
|
|
|
- tmp = ii << -arsh;
|
|
|
- }
|
|
|
- if (tmp == 0) {
|
|
|
- error = true;
|
|
|
- break;
|
|
|
- }
|
|
|
- a /= tmp;
|
|
|
+ b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
|
|
|
|
|
|
- brsh = qq_nbits - 11;
|
|
|
- if (brsh >= 0) {
|
|
|
- b = (qq << (31 - qq_nbits));
|
|
|
- tmp = ii >> brsh;
|
|
|
- } else {
|
|
|
- b = (qq << (31 - qq_nbits));
|
|
|
- tmp = ii << -brsh;
|
|
|
- }
|
|
|
- if (tmp == 0) {
|
|
|
- error = true;
|
|
|
- break;
|
|
|
- }
|
|
|
- b = int_sqrt(b / tmp - a * a) - (1 << 10);
|
|
|
+ seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
|
|
|
|
|
|
- if (i == 0 && (mask & 0x1)) {
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- new.a0 = a & 0x3FF;
|
|
|
- new.b0 = b & 0x3FF;
|
|
|
- } else {
|
|
|
- new.a0 = b & 0x3FF;
|
|
|
- new.b0 = a & 0x3FF;
|
|
|
- }
|
|
|
- } else if (i == 1 && (mask & 0x2)) {
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- new.a1 = a & 0x3FF;
|
|
|
- new.b1 = b & 0x3FF;
|
|
|
- } else {
|
|
|
- new.a1 = b & 0x3FF;
|
|
|
- new.b1 = a & 0x3FF;
|
|
|
- }
|
|
|
+ b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
|
|
|
+ if (iqmode) {
|
|
|
+ b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
|
|
|
+ b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
|
|
|
+ } else {
|
|
|
+ if (dac_test)
|
|
|
+ b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
|
|
|
+ else
|
|
|
+ b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
|
|
|
+ }
|
|
|
+ for (i = 0; i < 100; i++) {
|
|
|
+ if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
|
|
|
+ i = 0;
|
|
|
+ break;
|
|
|
}
|
|
|
+ udelay(10);
|
|
|
}
|
|
|
+ if (i)
|
|
|
+ b43err(dev->wl, "run samples timeout\n");
|
|
|
|
|
|
- if (error)
|
|
|
- new = old;
|
|
|
-
|
|
|
- b43_nphy_rx_iq_coeffs(dev, true, &new);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
|
|
|
-static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
|
|
|
+/**************************************************
|
|
|
+ * RSSI
|
|
|
+ **************************************************/
|
|
|
+
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
|
|
|
+static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
|
|
|
+ s8 offset, u8 core, u8 rail,
|
|
|
+ enum b43_nphy_rssi_type type)
|
|
|
{
|
|
|
- u16 array[4];
|
|
|
- b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
|
|
|
+ u16 tmp;
|
|
|
+ bool core1or5 = (core == 1) || (core == 5);
|
|
|
+ bool core2or5 = (core == 2) || (core == 5);
|
|
|
|
|
|
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
|
|
|
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
|
|
|
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
|
|
|
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
|
|
|
-}
|
|
|
+ offset = clamp_val(offset, -32, 31);
|
|
|
+ tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
|
|
|
-static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
|
|
|
- const u16 *clip_st)
|
|
|
-{
|
|
|
- b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
|
|
|
- b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
|
|
|
-}
|
|
|
+ if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
|
|
|
+ if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
|
|
|
+ if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
|
|
|
+ if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
|
|
|
-static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
|
|
|
-{
|
|
|
- clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
|
|
|
- clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
|
|
|
-}
|
|
|
+ if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
|
|
|
+ if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
|
|
|
+ if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
|
|
|
+ if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
|
|
|
-static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
|
|
|
-{
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- if (!init)
|
|
|
- return;
|
|
|
- if (0 /* FIXME */) {
|
|
|
- b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
|
|
|
- b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
|
|
|
- b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
|
|
|
- b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
|
|
|
- }
|
|
|
- } else {
|
|
|
- b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
|
|
|
- b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
|
|
|
+ if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
|
|
|
+ if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
|
|
|
+ if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
|
|
|
+ if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
|
|
|
|
|
|
- switch (dev->dev->bus_type) {
|
|
|
-#ifdef CONFIG_B43_BCMA
|
|
|
- case B43_BUS_BCMA:
|
|
|
- bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
|
|
|
- 0xFC00, 0xFC00);
|
|
|
- break;
|
|
|
-#endif
|
|
|
-#ifdef CONFIG_B43_SSB
|
|
|
- case B43_BUS_SSB:
|
|
|
- ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
|
|
|
- 0xFC00, 0xFC00);
|
|
|
- break;
|
|
|
-#endif
|
|
|
- }
|
|
|
+ if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
|
|
|
+ if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
|
|
|
+ if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
|
|
|
+ if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
|
|
|
|
|
|
- b43_write32(dev, B43_MMIO_MACCTL,
|
|
|
- b43_read32(dev, B43_MMIO_MACCTL) &
|
|
|
- ~B43_MACCTL_GPOUTSMSK);
|
|
|
- b43_write16(dev, B43_MMIO_GPIO_MASK,
|
|
|
- b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
|
|
|
- b43_write16(dev, B43_MMIO_GPIO_CONTROL,
|
|
|
- b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
|
|
|
+ if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
|
|
|
+ if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
|
|
|
+ if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
|
|
|
+ if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
|
|
|
|
|
|
- if (init) {
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
|
|
|
- }
|
|
|
- }
|
|
|
+ if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
|
|
|
+ if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
|
|
|
+
|
|
|
+ if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
|
|
|
+ if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
|
|
|
+ b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
|
|
|
-static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
|
|
|
+static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
|
|
|
{
|
|
|
- u16 tmp;
|
|
|
+ u8 i;
|
|
|
+ u16 reg, val;
|
|
|
|
|
|
- if (dev->dev->core_rev == 16)
|
|
|
- b43_mac_suspend(dev);
|
|
|
+ if (code == 0) {
|
|
|
+ b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
|
|
|
+ } else {
|
|
|
+ for (i = 0; i < 2; i++) {
|
|
|
+ if ((code == 1 && i == 1) || (code == 2 && !i))
|
|
|
+ continue;
|
|
|
|
|
|
- tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
|
|
|
- tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
|
|
|
- B43_NPHY_CLASSCTL_WAITEDEN);
|
|
|
- tmp &= ~mask;
|
|
|
- tmp |= (val & mask);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
|
|
|
+ reg = (i == 0) ?
|
|
|
+ B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
|
|
|
+ b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
|
|
|
|
|
|
- if (dev->dev->core_rev == 16)
|
|
|
- b43_mac_enable(dev);
|
|
|
+ if (type < 3) {
|
|
|
+ reg = (i == 0) ?
|
|
|
+ B43_NPHY_AFECTL_C1 :
|
|
|
+ B43_NPHY_AFECTL_C2;
|
|
|
+ b43_phy_maskset(dev, reg, 0xFCFF, 0);
|
|
|
|
|
|
- return tmp;
|
|
|
-}
|
|
|
+ reg = (i == 0) ?
|
|
|
+ B43_NPHY_RFCTL_LUT_TRSW_UP1 :
|
|
|
+ B43_NPHY_RFCTL_LUT_TRSW_UP2;
|
|
|
+ b43_phy_maskset(dev, reg, 0xFFC3, 0);
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
|
|
|
-static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
|
|
|
-{
|
|
|
- struct b43_phy *phy = &dev->phy;
|
|
|
- struct b43_phy_n *nphy = phy->n;
|
|
|
+ if (type == 0)
|
|
|
+ val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
|
|
|
+ else if (type == 1)
|
|
|
+ val = 16;
|
|
|
+ else
|
|
|
+ val = 32;
|
|
|
+ b43_phy_set(dev, reg, val);
|
|
|
|
|
|
- if (enable) {
|
|
|
- static const u16 clip[] = { 0xFFFF, 0xFFFF };
|
|
|
- if (nphy->deaf_count++ == 0) {
|
|
|
- nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
|
|
|
- b43_nphy_classifier(dev, 0x7, 0);
|
|
|
- b43_nphy_read_clip_detection(dev, nphy->clip_state);
|
|
|
- b43_nphy_write_clip_detection(dev, clip);
|
|
|
- }
|
|
|
- b43_nphy_reset_cca(dev);
|
|
|
- } else {
|
|
|
- if (--nphy->deaf_count == 0) {
|
|
|
- b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
|
|
|
- b43_nphy_write_clip_detection(dev, nphy->clip_state);
|
|
|
- }
|
|
|
- }
|
|
|
-}
|
|
|
+ reg = (i == 0) ?
|
|
|
+ B43_NPHY_TXF_40CO_B1S0 :
|
|
|
+ B43_NPHY_TXF_40CO_B32S1;
|
|
|
+ b43_phy_set(dev, reg, 0x0020);
|
|
|
+ } else {
|
|
|
+ if (type == 6)
|
|
|
+ val = 0x0100;
|
|
|
+ else if (type == 3)
|
|
|
+ val = 0x0200;
|
|
|
+ else
|
|
|
+ val = 0x0300;
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
|
|
|
-static void b43_nphy_stop_playback(struct b43_wldev *dev)
|
|
|
-{
|
|
|
- struct b43_phy_n *nphy = dev->phy.n;
|
|
|
- u16 tmp;
|
|
|
+ reg = (i == 0) ?
|
|
|
+ B43_NPHY_AFECTL_C1 :
|
|
|
+ B43_NPHY_AFECTL_C2;
|
|
|
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, 1);
|
|
|
+ b43_phy_maskset(dev, reg, 0xFCFF, val);
|
|
|
+ b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
|
|
|
|
|
|
- tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
|
|
|
- if (tmp & 0x1)
|
|
|
- b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
|
|
|
- else if (tmp & 0x2)
|
|
|
- b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
|
|
|
+ if (type != 3 && type != 6) {
|
|
|
+ enum ieee80211_band band =
|
|
|
+ b43_current_band(dev->wl);
|
|
|
|
|
|
- b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
|
|
|
+ if (b43_nphy_ipa(dev))
|
|
|
+ val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
|
|
|
+ else
|
|
|
+ val = 0x11;
|
|
|
+ reg = (i == 0) ? 0x2000 : 0x3000;
|
|
|
+ reg |= B2055_PADDRV;
|
|
|
+ b43_radio_write16(dev, reg, val);
|
|
|
|
|
|
- if (nphy->bb_mult_save & 0x80000000) {
|
|
|
- tmp = nphy->bb_mult_save & 0xFFFF;
|
|
|
- b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
|
|
|
- nphy->bb_mult_save = 0;
|
|
|
+ reg = (i == 0) ?
|
|
|
+ B43_NPHY_AFECTL_OVER1 :
|
|
|
+ B43_NPHY_AFECTL_OVER;
|
|
|
+ b43_phy_set(dev, reg, 0x0200);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
}
|
|
|
-
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, 0);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
|
|
|
-static void b43_nphy_spur_workaround(struct b43_wldev *dev)
|
|
|
+static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
|
|
|
{
|
|
|
- struct b43_phy_n *nphy = dev->phy.n;
|
|
|
-
|
|
|
- u8 channel = dev->phy.channel;
|
|
|
- int tone[2] = { 57, 58 };
|
|
|
- u32 noise[2] = { 0x3FF, 0x3FF };
|
|
|
+ u16 val;
|
|
|
|
|
|
- B43_WARN_ON(dev->phy.rev < 3);
|
|
|
+ if (type < 3)
|
|
|
+ val = 0;
|
|
|
+ else if (type == 6)
|
|
|
+ val = 1;
|
|
|
+ else if (type == 3)
|
|
|
+ val = 2;
|
|
|
+ else
|
|
|
+ val = 3;
|
|
|
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, 1);
|
|
|
+ val = (val << 12) | (val << 14);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
|
|
|
|
|
|
- if (nphy->gband_spurwar_en) {
|
|
|
- /* TODO: N PHY Adjust Analog Pfbw (7) */
|
|
|
- if (channel == 11 && dev->phy.is_40mhz)
|
|
|
- ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
|
|
|
- else
|
|
|
- ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
|
|
|
- /* TODO: N PHY Adjust CRS Min Power (0x1E) */
|
|
|
+ if (type < 3) {
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
|
|
|
+ (type + 1) << 4);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
|
|
|
+ (type + 1) << 4);
|
|
|
}
|
|
|
|
|
|
- if (nphy->aband_spurwar_en) {
|
|
|
- if (channel == 54) {
|
|
|
- tone[0] = 0x20;
|
|
|
- noise[0] = 0x25F;
|
|
|
- } else if (channel == 38 || channel == 102 || channel == 118) {
|
|
|
- if (0 /* FIXME */) {
|
|
|
- tone[0] = 0x20;
|
|
|
- noise[0] = 0x21F;
|
|
|
- } else {
|
|
|
- tone[0] = 0;
|
|
|
- noise[0] = 0;
|
|
|
- }
|
|
|
- } else if (channel == 134) {
|
|
|
- tone[0] = 0x20;
|
|
|
- noise[0] = 0x21F;
|
|
|
- } else if (channel == 151) {
|
|
|
- tone[0] = 0x10;
|
|
|
- noise[0] = 0x23F;
|
|
|
- } else if (channel == 153 || channel == 161) {
|
|
|
- tone[0] = 0x30;
|
|
|
- noise[0] = 0x23F;
|
|
|
- } else {
|
|
|
- tone[0] = 0;
|
|
|
- noise[0] = 0;
|
|
|
+ if (code == 0) {
|
|
|
+ b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
|
|
|
+ if (type < 3) {
|
|
|
+ b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
|
|
|
+ ~(B43_NPHY_RFCTL_CMD_RXEN |
|
|
|
+ B43_NPHY_RFCTL_CMD_CORESEL));
|
|
|
+ b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
|
|
|
+ ~(0x1 << 12 |
|
|
|
+ 0x1 << 5 |
|
|
|
+ 0x1 << 1 |
|
|
|
+ 0x1));
|
|
|
+ b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
|
|
|
+ ~B43_NPHY_RFCTL_CMD_START);
|
|
|
+ udelay(20);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
|
|
|
+ if (type < 3) {
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
|
|
|
+ ~(B43_NPHY_RFCTL_CMD_RXEN |
|
|
|
+ B43_NPHY_RFCTL_CMD_CORESEL),
|
|
|
+ (B43_NPHY_RFCTL_CMD_RXEN |
|
|
|
+ code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
|
|
|
+ b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
|
|
|
+ (0x1 << 12 |
|
|
|
+ 0x1 << 5 |
|
|
|
+ 0x1 << 1 |
|
|
|
+ 0x1));
|
|
|
+ b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
|
|
+ B43_NPHY_RFCTL_CMD_START);
|
|
|
+ udelay(20);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
|
|
|
}
|
|
|
-
|
|
|
- if (!tone[0] && !noise[0])
|
|
|
- ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
|
|
|
- else
|
|
|
- ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
|
|
|
}
|
|
|
-
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, 0);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
|
|
|
-static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
|
|
|
+static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
|
|
|
{
|
|
|
- struct b43_phy_n *nphy = dev->phy.n;
|
|
|
-
|
|
|
- u8 i;
|
|
|
- s16 tmp;
|
|
|
- u16 data[4];
|
|
|
- s16 gain[2];
|
|
|
- u16 minmax[2];
|
|
|
- static const u16 lna_gain[4] = { -2, 10, 19, 25 };
|
|
|
-
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, 1);
|
|
|
-
|
|
|
- if (nphy->gain_boost) {
|
|
|
- if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
|
|
|
- gain[0] = 6;
|
|
|
- gain[1] = 6;
|
|
|
- } else {
|
|
|
- tmp = 40370 - 315 * dev->phy.channel;
|
|
|
- gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
|
|
|
- tmp = 23242 - 224 * dev->phy.channel;
|
|
|
- gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
|
|
|
- }
|
|
|
- } else {
|
|
|
- gain[0] = 0;
|
|
|
- gain[1] = 0;
|
|
|
- }
|
|
|
+ if (dev->phy.rev >= 3)
|
|
|
+ b43_nphy_rev3_rssi_select(dev, code, type);
|
|
|
+ else
|
|
|
+ b43_nphy_rev2_rssi_select(dev, code, type);
|
|
|
+}
|
|
|
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
|
|
|
+static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
|
|
|
+{
|
|
|
+ int i;
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
- if (nphy->elna_gain_config) {
|
|
|
- data[0] = 19 + gain[i];
|
|
|
- data[1] = 25 + gain[i];
|
|
|
- data[2] = 25 + gain[i];
|
|
|
- data[3] = 25 + gain[i];
|
|
|
+ if (type == 2) {
|
|
|
+ if (i == 0) {
|
|
|
+ b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
|
|
|
+ 0xFC, buf[0]);
|
|
|
+ b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
|
|
|
+ 0xFC, buf[1]);
|
|
|
+ } else {
|
|
|
+ b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
|
|
|
+ 0xFC, buf[2 * i]);
|
|
|
+ b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
|
|
|
+ 0xFC, buf[2 * i + 1]);
|
|
|
+ }
|
|
|
} else {
|
|
|
- data[0] = lna_gain[0] + gain[i];
|
|
|
- data[1] = lna_gain[1] + gain[i];
|
|
|
- data[2] = lna_gain[2] + gain[i];
|
|
|
- data[3] = lna_gain[3] + gain[i];
|
|
|
+ if (i == 0)
|
|
|
+ b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
|
|
|
+ 0xF3, buf[0] << 2);
|
|
|
+ else
|
|
|
+ b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
|
|
|
+ 0xF3, buf[2 * i + 1] << 2);
|
|
|
}
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
|
|
|
-
|
|
|
- minmax[i] = 23 + gain[i];
|
|
|
}
|
|
|
-
|
|
|
- b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
|
|
|
- minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
|
|
|
- minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
|
|
|
-
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, 0);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
|
|
|
-static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
|
|
|
+static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
|
|
|
+ u8 nsamp)
|
|
|
{
|
|
|
- struct b43_phy_n *nphy = dev->phy.n;
|
|
|
- struct ssb_sprom *sprom = dev->dev->bus_sprom;
|
|
|
-
|
|
|
- /* PHY rev 0, 1, 2 */
|
|
|
- u8 i, j;
|
|
|
- u8 code;
|
|
|
- u16 tmp;
|
|
|
- u8 rfseq_events[3] = { 6, 8, 7 };
|
|
|
- u8 rfseq_delays[3] = { 10, 30, 1 };
|
|
|
-
|
|
|
- /* PHY rev >= 3 */
|
|
|
- bool ghz5;
|
|
|
- bool ext_lna;
|
|
|
- u16 rssi_gain;
|
|
|
- struct nphy_gain_ctl_workaround_entry *e;
|
|
|
- u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
|
|
|
- u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
|
|
|
+ int i;
|
|
|
+ int out;
|
|
|
+ u16 save_regs_phy[9];
|
|
|
+ u16 s[2];
|
|
|
|
|
|
if (dev->phy.rev >= 3) {
|
|
|
- /* Prepare values */
|
|
|
- ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
|
|
|
- & B43_NPHY_BANDCTL_5GHZ;
|
|
|
- ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
|
|
|
- e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
|
|
|
- if (ghz5 && dev->phy.rev >= 5)
|
|
|
- rssi_gain = 0x90;
|
|
|
- else
|
|
|
- rssi_gain = 0x50;
|
|
|
-
|
|
|
- b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
|
|
|
-
|
|
|
- /* Set Clip 2 detect */
|
|
|
- b43_phy_set(dev, B43_NPHY_C1_CGAINI,
|
|
|
- B43_NPHY_C1_CGAINI_CL2DETECT);
|
|
|
- b43_phy_set(dev, B43_NPHY_C2_CGAINI,
|
|
|
- B43_NPHY_C2_CGAINI_CL2DETECT);
|
|
|
-
|
|
|
- b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
|
|
|
- 0x17);
|
|
|
- b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
|
|
|
- 0x17);
|
|
|
- b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
|
|
|
- b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
|
|
|
- b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
|
|
|
- b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
|
|
|
- b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
|
|
|
- rssi_gain);
|
|
|
- b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
|
|
|
- rssi_gain);
|
|
|
- b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
|
|
|
- 0x17);
|
|
|
- b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
|
|
|
- 0x17);
|
|
|
- b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
|
|
|
- b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
|
|
|
-
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
|
|
|
-
|
|
|
- b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
|
|
|
- b43_phy_write(dev, 0x2A7, e->init_gain);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
|
|
|
- e->rfseq_init);
|
|
|
- b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
|
|
|
-
|
|
|
- /* TODO: check defines. Do not match variables names */
|
|
|
- b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
|
|
|
- b43_phy_write(dev, 0x2A9, e->cliphi_gain);
|
|
|
- b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
|
|
|
- b43_phy_write(dev, 0x2AB, e->clipmd_gain);
|
|
|
- b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
|
|
|
- b43_phy_write(dev, 0x2AD, e->cliplo_gain);
|
|
|
-
|
|
|
- b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
|
|
|
- b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
|
|
|
- b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
|
|
|
- b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
|
|
|
- b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
|
|
|
- ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
|
|
|
- ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
|
|
|
- b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
|
|
|
+ save_regs_phy[0] = b43_phy_read(dev,
|
|
|
+ B43_NPHY_RFCTL_LUT_TRSW_UP1);
|
|
|
+ save_regs_phy[1] = b43_phy_read(dev,
|
|
|
+ B43_NPHY_RFCTL_LUT_TRSW_UP2);
|
|
|
+ save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
|
|
|
+ save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
|
|
|
+ save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
|
|
|
+ save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
|
|
|
+ save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
|
|
|
+ save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
|
|
|
+ save_regs_phy[8] = 0;
|
|
|
} else {
|
|
|
- /* Set Clip 2 detect */
|
|
|
- b43_phy_set(dev, B43_NPHY_C1_CGAINI,
|
|
|
- B43_NPHY_C1_CGAINI_CL2DETECT);
|
|
|
- b43_phy_set(dev, B43_NPHY_C2_CGAINI,
|
|
|
- B43_NPHY_C2_CGAINI_CL2DETECT);
|
|
|
-
|
|
|
- /* Set narrowband clip threshold */
|
|
|
- b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
|
|
|
- b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
|
|
|
-
|
|
|
- if (!dev->phy.is_40mhz) {
|
|
|
- /* Set dwell lengths */
|
|
|
- b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
|
|
|
- b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
|
|
|
- b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
|
|
|
- b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
|
|
|
- }
|
|
|
+ save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
|
|
|
+ save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
|
|
|
+ save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
|
|
|
+ save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
|
|
|
+ save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
|
|
|
+ save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
|
|
|
+ save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
|
|
|
+ save_regs_phy[7] = 0;
|
|
|
+ save_regs_phy[8] = 0;
|
|
|
+ }
|
|
|
|
|
|
- /* Set wideband clip 2 threshold */
|
|
|
- b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
|
|
|
- ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
|
|
|
- 21);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
|
|
|
- ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
|
|
|
- 21);
|
|
|
-
|
|
|
- if (!dev->phy.is_40mhz) {
|
|
|
- b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
|
|
|
- ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
|
|
|
- ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
|
|
|
- ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
|
|
|
- ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
|
|
|
- }
|
|
|
+ b43_nphy_rssi_select(dev, 5, type);
|
|
|
|
|
|
- b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
|
|
|
+ if (dev->phy.rev < 2) {
|
|
|
+ save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
|
|
|
+ b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
|
|
|
+ }
|
|
|
|
|
|
- if (nphy->gain_boost) {
|
|
|
- if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
|
|
|
- dev->phy.is_40mhz)
|
|
|
- code = 4;
|
|
|
- else
|
|
|
- code = 5;
|
|
|
+ for (i = 0; i < 4; i++)
|
|
|
+ buf[i] = 0;
|
|
|
+
|
|
|
+ for (i = 0; i < nsamp; i++) {
|
|
|
+ if (dev->phy.rev < 2) {
|
|
|
+ s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
|
|
|
+ s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
|
|
|
} else {
|
|
|
- code = dev->phy.is_40mhz ? 6 : 7;
|
|
|
+ s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
|
|
|
+ s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
|
|
|
}
|
|
|
|
|
|
- /* Set HPVGA2 index */
|
|
|
- b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
|
|
|
- ~B43_NPHY_C1_INITGAIN_HPVGA2,
|
|
|
- code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
|
|
|
- ~B43_NPHY_C2_INITGAIN_HPVGA2,
|
|
|
- code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
|
|
|
+ buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
|
|
|
+ buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
|
|
|
+ buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
|
|
|
+ buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
|
|
|
+ }
|
|
|
+ out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
|
|
|
+ (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
|
|
|
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
|
|
|
- /* specs say about 2 loops, but wl does 4 */
|
|
|
- for (i = 0; i < 4; i++)
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
|
|
|
- (code << 8 | 0x7C));
|
|
|
+ if (dev->phy.rev < 2)
|
|
|
+ b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
|
|
|
|
|
|
- b43_nphy_adjust_lna_gain_table(dev);
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
|
|
|
+ save_regs_phy[0]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
|
|
|
+ save_regs_phy[1]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
|
|
|
+ } else {
|
|
|
+ b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
|
|
|
+ }
|
|
|
|
|
|
- if (nphy->elna_gain_config) {
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
|
|
|
-
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
|
|
|
-
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
|
|
|
- /* specs say about 2 loops, but wl does 4 */
|
|
|
- for (i = 0; i < 4; i++)
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
|
|
|
- (code << 8 | 0x74));
|
|
|
- }
|
|
|
+ return out;
|
|
|
+}
|
|
|
|
|
|
- if (dev->phy.rev == 2) {
|
|
|
- for (i = 0; i < 4; i++) {
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
|
|
|
- (0x0400 * i) + 0x0020);
|
|
|
- for (j = 0; j < 21; j++) {
|
|
|
- tmp = j * (i < 2 ? 3 : 1);
|
|
|
- b43_phy_write(dev,
|
|
|
- B43_NPHY_TABLE_DATALO, tmp);
|
|
|
- }
|
|
|
- }
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
|
|
|
+static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
|
|
|
+{
|
|
|
+ int i, j;
|
|
|
+ u8 state[4];
|
|
|
+ u8 code, val;
|
|
|
+ u16 class, override;
|
|
|
+ u8 regs_save_radio[2];
|
|
|
+ u16 regs_save_phy[2];
|
|
|
+
|
|
|
+ s8 offset[4];
|
|
|
+ u8 core;
|
|
|
+ u8 rail;
|
|
|
+
|
|
|
+ u16 clip_state[2];
|
|
|
+ u16 clip_off[2] = { 0xFFFF, 0xFFFF };
|
|
|
+ s32 results_min[4] = { };
|
|
|
+ u8 vcm_final[4] = { };
|
|
|
+ s32 results[4][4] = { };
|
|
|
+ s32 miniq[4][2] = { };
|
|
|
+
|
|
|
+ if (type == 2) {
|
|
|
+ code = 0;
|
|
|
+ val = 6;
|
|
|
+ } else if (type < 2) {
|
|
|
+ code = 25;
|
|
|
+ val = 4;
|
|
|
+ } else {
|
|
|
+ B43_WARN_ON(1);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ class = b43_nphy_classifier(dev, 0, 0);
|
|
|
+ b43_nphy_classifier(dev, 7, 4);
|
|
|
+ b43_nphy_read_clip_detection(dev, clip_state);
|
|
|
+ b43_nphy_write_clip_detection(dev, clip_off);
|
|
|
+
|
|
|
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
|
|
|
+ override = 0x140;
|
|
|
+ else
|
|
|
+ override = 0x110;
|
|
|
+
|
|
|
+ regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
|
|
|
+ regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
|
|
|
+ b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
|
|
|
+
|
|
|
+ regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
|
|
|
+ regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
|
|
|
+ b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
|
|
|
+
|
|
|
+ state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
|
|
|
+ state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
|
|
|
+ b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
|
|
|
+ b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
|
|
|
+ state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
|
|
|
+ state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
|
|
|
+
|
|
|
+ b43_nphy_rssi_select(dev, 5, type);
|
|
|
+ b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
|
|
|
+ b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
|
|
|
+
|
|
|
+ for (i = 0; i < 4; i++) {
|
|
|
+ u8 tmp[4];
|
|
|
+ for (j = 0; j < 4; j++)
|
|
|
+ tmp[j] = i;
|
|
|
+ if (type != 1)
|
|
|
+ b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
|
|
|
+ b43_nphy_poll_rssi(dev, type, results[i], 8);
|
|
|
+ if (type < 2)
|
|
|
+ for (j = 0; j < 2; j++)
|
|
|
+ miniq[i][j] = min(results[i][2 * j],
|
|
|
+ results[i][2 * j + 1]);
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = 0; i < 4; i++) {
|
|
|
+ s32 mind = 40;
|
|
|
+ u8 minvcm = 0;
|
|
|
+ s32 minpoll = 249;
|
|
|
+ s32 curr;
|
|
|
+ for (j = 0; j < 4; j++) {
|
|
|
+ if (type == 2)
|
|
|
+ curr = abs(results[j][i]);
|
|
|
+ else
|
|
|
+ curr = abs(miniq[j][i / 2] - code * 8);
|
|
|
+
|
|
|
+ if (curr < mind) {
|
|
|
+ mind = curr;
|
|
|
+ minvcm = j;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (results[j][i] < minpoll)
|
|
|
+ minpoll = results[j][i];
|
|
|
}
|
|
|
+ results_min[i] = minpoll;
|
|
|
+ vcm_final[i] = minvcm;
|
|
|
+ }
|
|
|
|
|
|
- b43_nphy_set_rf_sequence(dev, 5,
|
|
|
- rfseq_events, rfseq_delays, 3);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
|
|
|
- ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
|
|
|
- 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
|
|
|
+ if (type != 1)
|
|
|
+ b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
|
|
|
|
|
|
- if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
|
|
|
- b43_phy_maskset(dev, B43_PHY_N(0xC5D),
|
|
|
- 0xFF80, 4);
|
|
|
+ for (i = 0; i < 4; i++) {
|
|
|
+ offset[i] = (code * 8) - results[vcm_final[i]][i];
|
|
|
+
|
|
|
+ if (offset[i] < 0)
|
|
|
+ offset[i] = -((abs(offset[i]) + 4) / 8);
|
|
|
+ else
|
|
|
+ offset[i] = (offset[i] + 4) / 8;
|
|
|
+
|
|
|
+ if (results_min[i] == 248)
|
|
|
+ offset[i] = code - 32;
|
|
|
+
|
|
|
+ core = (i / 2) ? 2 : 1;
|
|
|
+ rail = (i % 2) ? 1 : 0;
|
|
|
+
|
|
|
+ b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
|
|
|
+ type);
|
|
|
+ }
|
|
|
+
|
|
|
+ b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
|
|
|
+ b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
|
|
|
+
|
|
|
+ switch (state[2]) {
|
|
|
+ case 1:
|
|
|
+ b43_nphy_rssi_select(dev, 1, 2);
|
|
|
+ break;
|
|
|
+ case 4:
|
|
|
+ b43_nphy_rssi_select(dev, 1, 0);
|
|
|
+ break;
|
|
|
+ case 2:
|
|
|
+ b43_nphy_rssi_select(dev, 1, 1);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ b43_nphy_rssi_select(dev, 1, 1);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ switch (state[3]) {
|
|
|
+ case 1:
|
|
|
+ b43_nphy_rssi_select(dev, 2, 2);
|
|
|
+ break;
|
|
|
+ case 4:
|
|
|
+ b43_nphy_rssi_select(dev, 2, 0);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ b43_nphy_rssi_select(dev, 2, 1);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ b43_nphy_rssi_select(dev, 0, type);
|
|
|
+
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
|
|
|
+ b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
|
|
|
+ b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
|
|
|
+
|
|
|
+ b43_nphy_classifier(dev, 7, class);
|
|
|
+ b43_nphy_write_clip_detection(dev, clip_state);
|
|
|
+ /* Specs don't say about reset here, but it makes wl and b43 dumps
|
|
|
+ identical, it really seems wl performs this */
|
|
|
+ b43_nphy_reset_cca(dev);
|
|
|
+}
|
|
|
+
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
|
|
|
+static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ /* TODO */
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * RSSI Calibration
|
|
|
+ * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
|
|
|
+ */
|
|
|
+static void b43_nphy_rssi_cal(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ b43_nphy_rev3_rssi_cal(dev);
|
|
|
+ } else {
|
|
|
+ b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
|
|
|
+ b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
|
|
|
+ b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/**************************************************
|
|
|
+ * Workarounds
|
|
|
+ **************************************************/
|
|
|
+
|
|
|
+static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ struct ssb_sprom *sprom = dev->dev->bus_sprom;
|
|
|
+
|
|
|
+ bool ghz5;
|
|
|
+ bool ext_lna;
|
|
|
+ u16 rssi_gain;
|
|
|
+ struct nphy_gain_ctl_workaround_entry *e;
|
|
|
+ u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
|
|
|
+ u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
|
|
|
+
|
|
|
+ /* Prepare values */
|
|
|
+ ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
|
|
|
+ & B43_NPHY_BANDCTL_5GHZ;
|
|
|
+ ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
|
|
|
+ e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
|
|
|
+ if (ghz5 && dev->phy.rev >= 5)
|
|
|
+ rssi_gain = 0x90;
|
|
|
+ else
|
|
|
+ rssi_gain = 0x50;
|
|
|
+
|
|
|
+ b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
|
|
|
+
|
|
|
+ /* Set Clip 2 detect */
|
|
|
+ b43_phy_set(dev, B43_NPHY_C1_CGAINI,
|
|
|
+ B43_NPHY_C1_CGAINI_CL2DETECT);
|
|
|
+ b43_phy_set(dev, B43_NPHY_C2_CGAINI,
|
|
|
+ B43_NPHY_C2_CGAINI_CL2DETECT);
|
|
|
+
|
|
|
+ b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
|
|
|
+ 0x17);
|
|
|
+ b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
|
|
|
+ 0x17);
|
|
|
+ b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
|
|
|
+ b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
|
|
|
+ b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
|
|
|
+ b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
|
|
|
+ b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
|
|
|
+ rssi_gain);
|
|
|
+ b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
|
|
|
+ rssi_gain);
|
|
|
+ b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
|
|
|
+ 0x17);
|
|
|
+ b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
|
|
|
+ 0x17);
|
|
|
+ b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
|
|
|
+ b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
|
|
|
+
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
|
|
|
+
|
|
|
+ b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
|
|
|
+ b43_phy_write(dev, 0x2A7, e->init_gain);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
|
|
|
+ e->rfseq_init);
|
|
|
+ b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
|
|
|
+
|
|
|
+ /* TODO: check defines. Do not match variables names */
|
|
|
+ b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
|
|
|
+ b43_phy_write(dev, 0x2A9, e->cliphi_gain);
|
|
|
+ b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
|
|
|
+ b43_phy_write(dev, 0x2AB, e->clipmd_gain);
|
|
|
+ b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
|
|
|
+ b43_phy_write(dev, 0x2AD, e->cliplo_gain);
|
|
|
+
|
|
|
+ b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
|
|
|
+ b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
|
|
|
+ b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
|
|
|
+ b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
|
|
|
+ b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
|
|
|
+ ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
|
|
|
+ ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
|
|
|
+ b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
|
|
|
+}
|
|
|
+
|
|
|
+static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ struct b43_phy_n *nphy = dev->phy.n;
|
|
|
+
|
|
|
+ u8 i, j;
|
|
|
+ u8 code;
|
|
|
+ u16 tmp;
|
|
|
+ u8 rfseq_events[3] = { 6, 8, 7 };
|
|
|
+ u8 rfseq_delays[3] = { 10, 30, 1 };
|
|
|
+
|
|
|
+ /* Set Clip 2 detect */
|
|
|
+ b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
|
|
|
+ b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
|
|
|
+
|
|
|
+ /* Set narrowband clip threshold */
|
|
|
+ b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
|
|
|
+ b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
|
|
|
+
|
|
|
+ if (!dev->phy.is_40mhz) {
|
|
|
+ /* Set dwell lengths */
|
|
|
+ b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
|
|
|
+ b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
|
|
|
+ b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
|
|
|
+ b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Set wideband clip 2 threshold */
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
|
|
|
+ ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
|
|
|
+ ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
|
|
|
+
|
|
|
+ if (!dev->phy.is_40mhz) {
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
|
|
|
+ ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
|
|
|
+ ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
|
|
|
+ ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
|
|
|
+ ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
|
|
|
+ }
|
|
|
+
|
|
|
+ b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
|
|
|
+
|
|
|
+ if (nphy->gain_boost) {
|
|
|
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
|
|
|
+ dev->phy.is_40mhz)
|
|
|
+ code = 4;
|
|
|
+ else
|
|
|
+ code = 5;
|
|
|
+ } else {
|
|
|
+ code = dev->phy.is_40mhz ? 6 : 7;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Set HPVGA2 index */
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
|
|
|
+ code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
|
|
|
+ code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
|
|
|
+
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
|
|
|
+ /* specs say about 2 loops, but wl does 4 */
|
|
|
+ for (i = 0; i < 4; i++)
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
|
|
|
+
|
|
|
+ b43_nphy_adjust_lna_gain_table(dev);
|
|
|
+
|
|
|
+ if (nphy->elna_gain_config) {
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
|
|
|
+
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
|
|
|
+
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
|
|
|
+ /* specs say about 2 loops, but wl does 4 */
|
|
|
+ for (i = 0; i < 4; i++)
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
|
|
|
+ (code << 8 | 0x74));
|
|
|
+ }
|
|
|
+
|
|
|
+ if (dev->phy.rev == 2) {
|
|
|
+ for (i = 0; i < 4; i++) {
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
|
|
|
+ (0x0400 * i) + 0x0020);
|
|
|
+ for (j = 0; j < 21; j++) {
|
|
|
+ tmp = j * (i < 2 ? 3 : 1);
|
|
|
+ b43_phy_write(dev,
|
|
|
+ B43_NPHY_TABLE_DATALO, tmp);
|
|
|
+ }
|
|
|
+ }
|
|
|
}
|
|
|
+
|
|
|
+ b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
|
|
|
+ ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
|
|
|
+ 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
|
|
|
+
|
|
|
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
|
|
|
+ b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
|
|
|
+}
|
|
|
+
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
|
|
|
+static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ if (dev->phy.rev >= 3)
|
|
|
+ b43_nphy_gain_ctl_workarounds_rev3plus(dev);
|
|
|
+ else
|
|
|
+ b43_nphy_gain_ctl_workarounds_rev1_2(dev);
|
|
|
}
|
|
|
|
|
|
static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
|
|
@@ -1660,7 +1765,7 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
|
|
|
b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
|
|
|
b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
|
|
|
|
|
|
- b43_nphy_gain_ctrl_workarounds(dev);
|
|
|
+ b43_nphy_gain_ctl_workarounds(dev);
|
|
|
|
|
|
b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
|
|
|
b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
|
|
@@ -1763,7 +1868,7 @@ static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
|
|
|
b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
|
|
|
b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
|
|
|
|
|
|
- b43_nphy_gain_ctrl_workarounds(dev);
|
|
|
+ b43_nphy_gain_ctl_workarounds(dev);
|
|
|
|
|
|
if (dev->phy.rev < 2) {
|
|
|
if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
|
|
@@ -1823,984 +1928,811 @@ static void b43_nphy_workarounds(struct b43_wldev *dev)
|
|
|
b43_nphy_stay_in_carrier_search(dev, 0);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
|
|
|
-static int b43_nphy_load_samples(struct b43_wldev *dev,
|
|
|
- struct b43_c32 *samples, u16 len) {
|
|
|
- struct b43_phy_n *nphy = dev->phy.n;
|
|
|
- u16 i;
|
|
|
- u32 *data;
|
|
|
-
|
|
|
- data = kzalloc(len * sizeof(u32), GFP_KERNEL);
|
|
|
- if (!data) {
|
|
|
- b43err(dev->wl, "allocation for samples loading failed\n");
|
|
|
- return -ENOMEM;
|
|
|
- }
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, 1);
|
|
|
+/**************************************************
|
|
|
+ * Tx and Rx
|
|
|
+ **************************************************/
|
|
|
|
|
|
- for (i = 0; i < len; i++) {
|
|
|
- data[i] = (samples[i].i & 0x3FF << 10);
|
|
|
- data[i] |= samples[i].q & 0x3FF;
|
|
|
- }
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
|
|
|
-
|
|
|
- kfree(data);
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, 0);
|
|
|
- return 0;
|
|
|
+void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
|
|
|
+{//TODO
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
|
|
|
-static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
|
|
|
- bool test)
|
|
|
-{
|
|
|
- int i;
|
|
|
- u16 bw, len, rot, angle;
|
|
|
- struct b43_c32 *samples;
|
|
|
-
|
|
|
+static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
|
|
|
+{//TODO
|
|
|
+}
|
|
|
|
|
|
- bw = (dev->phy.is_40mhz) ? 40 : 20;
|
|
|
- len = bw << 3;
|
|
|
+static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
|
|
|
+ bool ignore_tssi)
|
|
|
+{//TODO
|
|
|
+ return B43_TXPWR_RES_DONE;
|
|
|
+}
|
|
|
|
|
|
- if (test) {
|
|
|
- if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
|
|
|
- bw = 82;
|
|
|
- else
|
|
|
- bw = 80;
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
|
|
|
+static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
|
|
|
+{
|
|
|
+ struct b43_phy_n *nphy = dev->phy.n;
|
|
|
+ u8 i;
|
|
|
+ u16 bmask, val, tmp;
|
|
|
+ enum ieee80211_band band = b43_current_band(dev->wl);
|
|
|
|
|
|
- if (dev->phy.is_40mhz)
|
|
|
- bw <<= 1;
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, 1);
|
|
|
|
|
|
- len = bw << 1;
|
|
|
- }
|
|
|
+ nphy->txpwrctrl = enable;
|
|
|
+ if (!enable) {
|
|
|
+ if (dev->phy.rev >= 3 &&
|
|
|
+ (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
|
|
|
+ (B43_NPHY_TXPCTL_CMD_COEFF |
|
|
|
+ B43_NPHY_TXPCTL_CMD_HWPCTLEN |
|
|
|
+ B43_NPHY_TXPCTL_CMD_PCTLEN))) {
|
|
|
+ /* We disable enabled TX pwr ctl, save it's state */
|
|
|
+ nphy->tx_pwr_idx[0] = b43_phy_read(dev,
|
|
|
+ B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
|
|
|
+ nphy->tx_pwr_idx[1] = b43_phy_read(dev,
|
|
|
+ B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
|
|
|
+ }
|
|
|
|
|
|
- samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
|
|
|
- if (!samples) {
|
|
|
- b43err(dev->wl, "allocation for samples generation failed\n");
|
|
|
- return 0;
|
|
|
- }
|
|
|
- rot = (((freq * 36) / bw) << 16) / 100;
|
|
|
- angle = 0;
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
|
|
|
+ for (i = 0; i < 84; i++)
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
|
|
|
|
|
|
- for (i = 0; i < len; i++) {
|
|
|
- samples[i] = b43_cordic(angle);
|
|
|
- angle += rot;
|
|
|
- samples[i].q = CORDIC_CONVERT(samples[i].q * max);
|
|
|
- samples[i].i = CORDIC_CONVERT(samples[i].i * max);
|
|
|
- }
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
|
|
|
+ for (i = 0; i < 84; i++)
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
|
|
|
|
|
|
- i = b43_nphy_load_samples(dev, samples, len);
|
|
|
- kfree(samples);
|
|
|
- return (i < 0) ? 0 : len;
|
|
|
-}
|
|
|
+ tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
|
|
|
+ if (dev->phy.rev >= 3)
|
|
|
+ tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
|
|
|
+ b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
|
|
|
-static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
|
|
|
- u16 wait, bool iqmode, bool dac_test)
|
|
|
-{
|
|
|
- struct b43_phy_n *nphy = dev->phy.n;
|
|
|
- int i;
|
|
|
- u16 seq_mode;
|
|
|
- u32 tmp;
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
|
|
|
+ b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
|
|
|
+ } else {
|
|
|
+ b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
|
|
|
+ }
|
|
|
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, true);
|
|
|
+ if (dev->phy.rev == 2)
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
|
|
|
+ ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
|
|
|
+ else if (dev->phy.rev < 2)
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
|
|
|
+ ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
|
|
|
|
|
|
- if ((nphy->bb_mult_save & 0x80000000) == 0) {
|
|
|
- tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
|
|
|
- nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
|
|
|
- }
|
|
|
+ if (dev->phy.rev < 2 && dev->phy.is_40mhz)
|
|
|
+ b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
|
|
|
+ } else {
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
|
|
|
+ nphy->adj_pwr_tbl);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
|
|
|
+ nphy->adj_pwr_tbl);
|
|
|
|
|
|
- if (!dev->phy.is_40mhz)
|
|
|
- tmp = 0x6464;
|
|
|
- else
|
|
|
- tmp = 0x4747;
|
|
|
- b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
|
|
|
+ bmask = B43_NPHY_TXPCTL_CMD_COEFF |
|
|
|
+ B43_NPHY_TXPCTL_CMD_HWPCTLEN;
|
|
|
+ /* wl does useless check for "enable" param here */
|
|
|
+ val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
|
|
|
+ if (val)
|
|
|
+ val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
|
|
|
+ }
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
|
|
|
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, false);
|
|
|
+ if (band == IEEE80211_BAND_5GHZ) {
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
|
|
|
+ ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
|
|
|
+ if (dev->phy.rev > 1)
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
|
|
|
+ ~B43_NPHY_TXPCTL_INIT_PIDXI1,
|
|
|
+ 0x64);
|
|
|
+ }
|
|
|
|
|
|
- b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ if (nphy->tx_pwr_idx[0] != 128 &&
|
|
|
+ nphy->tx_pwr_idx[1] != 128) {
|
|
|
+ /* Recover TX pwr ctl state */
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
|
|
|
+ ~B43_NPHY_TXPCTL_CMD_INIT,
|
|
|
+ nphy->tx_pwr_idx[0]);
|
|
|
+ if (dev->phy.rev > 1)
|
|
|
+ b43_phy_maskset(dev,
|
|
|
+ B43_NPHY_TXPCTL_INIT,
|
|
|
+ ~0xff, nphy->tx_pwr_idx[1]);
|
|
|
+ }
|
|
|
+ }
|
|
|
|
|
|
- if (loops != 0xFFFF)
|
|
|
- b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
|
|
|
- else
|
|
|
- b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
|
|
|
+ } else {
|
|
|
+ b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
|
|
|
+ }
|
|
|
|
|
|
- b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
|
|
|
+ if (dev->phy.rev == 2)
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
|
|
|
+ else if (dev->phy.rev < 2)
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
|
|
|
|
|
|
- seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
|
|
|
+ if (dev->phy.rev < 2 && dev->phy.is_40mhz)
|
|
|
+ b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
|
|
|
|
|
|
- b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
|
|
|
- if (iqmode) {
|
|
|
- b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
|
|
|
- b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
|
|
|
- } else {
|
|
|
- if (dac_test)
|
|
|
- b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
|
|
|
- else
|
|
|
- b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
|
|
|
- }
|
|
|
- for (i = 0; i < 100; i++) {
|
|
|
- if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
|
|
|
- i = 0;
|
|
|
- break;
|
|
|
+ if (b43_nphy_ipa(dev)) {
|
|
|
+ b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
|
|
|
}
|
|
|
- udelay(10);
|
|
|
}
|
|
|
- if (i)
|
|
|
- b43err(dev->wl, "run samples timeout\n");
|
|
|
-
|
|
|
- b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
|
|
|
-}
|
|
|
|
|
|
-/*
|
|
|
- * Transmits a known value for LO calibration
|
|
|
- * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
|
|
|
- */
|
|
|
-static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
|
|
|
- bool iqmode, bool dac_test)
|
|
|
-{
|
|
|
- u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
|
|
|
- if (samp == 0)
|
|
|
- return -1;
|
|
|
- b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
|
|
|
- return 0;
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, 0);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
|
|
|
-static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
|
|
|
+static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
|
|
|
{
|
|
|
struct b43_phy_n *nphy = dev->phy.n;
|
|
|
- int i, j;
|
|
|
- u32 tmp;
|
|
|
- u32 cur_real, cur_imag, real_part, imag_part;
|
|
|
+ struct ssb_sprom *sprom = dev->dev->bus_sprom;
|
|
|
|
|
|
- u16 buffer[7];
|
|
|
+ u8 txpi[2], bbmult, i;
|
|
|
+ u16 tmp, radio_gain, dac_gain;
|
|
|
+ u16 freq = dev->phy.channel_freq;
|
|
|
+ u32 txgain;
|
|
|
+ /* u32 gaintbl; rev3+ */
|
|
|
|
|
|
if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, true);
|
|
|
-
|
|
|
- b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
|
|
|
-
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- tmp = ((buffer[i * 2] & 0x3FF) << 10) |
|
|
|
- (buffer[i * 2 + 1] & 0x3FF);
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
|
|
|
- (((i + 26) << 10) | 320));
|
|
|
- for (j = 0; j < 128; j++) {
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
|
|
|
- ((tmp >> 16) & 0xFFFF));
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
|
|
|
- (tmp & 0xFFFF));
|
|
|
- }
|
|
|
- }
|
|
|
-
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- tmp = buffer[5 + i];
|
|
|
- real_part = (tmp >> 8) & 0xFF;
|
|
|
- imag_part = (tmp & 0xFF);
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
|
|
|
- (((i + 26) << 10) | 448));
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, 1);
|
|
|
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- cur_real = real_part;
|
|
|
- cur_imag = imag_part;
|
|
|
- tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
|
|
|
- }
|
|
|
-
|
|
|
- for (j = 0; j < 128; j++) {
|
|
|
- if (dev->phy.rev < 3) {
|
|
|
- cur_real = (real_part * loscale[j] + 128) >> 8;
|
|
|
- cur_imag = (imag_part * loscale[j] + 128) >> 8;
|
|
|
- tmp = ((cur_real & 0xFF) << 8) |
|
|
|
- (cur_imag & 0xFF);
|
|
|
- }
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
|
|
|
- ((tmp >> 16) & 0xFFFF));
|
|
|
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
|
|
|
- (tmp & 0xFFFF));
|
|
|
+ if (dev->phy.rev >= 7) {
|
|
|
+ txpi[0] = txpi[1] = 30;
|
|
|
+ } else if (dev->phy.rev >= 3) {
|
|
|
+ txpi[0] = 40;
|
|
|
+ txpi[1] = 40;
|
|
|
+ } else if (sprom->revision < 4) {
|
|
|
+ txpi[0] = 72;
|
|
|
+ txpi[1] = 72;
|
|
|
+ } else {
|
|
|
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
|
|
|
+ txpi[0] = sprom->txpid2g[0];
|
|
|
+ txpi[1] = sprom->txpid2g[1];
|
|
|
+ } else if (freq >= 4900 && freq < 5100) {
|
|
|
+ txpi[0] = sprom->txpid5gl[0];
|
|
|
+ txpi[1] = sprom->txpid5gl[1];
|
|
|
+ } else if (freq >= 5100 && freq < 5500) {
|
|
|
+ txpi[0] = sprom->txpid5g[0];
|
|
|
+ txpi[1] = sprom->txpid5g[1];
|
|
|
+ } else if (freq >= 5500) {
|
|
|
+ txpi[0] = sprom->txpid5gh[0];
|
|
|
+ txpi[1] = sprom->txpid5gh[1];
|
|
|
+ } else {
|
|
|
+ txpi[0] = 91;
|
|
|
+ txpi[1] = 91;
|
|
|
}
|
|
|
}
|
|
|
+ if (dev->phy.rev < 7 &&
|
|
|
+ (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 10))
|
|
|
+ txpi[0] = txpi[1] = 91;
|
|
|
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- b43_shm_write16(dev, B43_SHM_SHARED,
|
|
|
- B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
|
|
|
- b43_shm_write16(dev, B43_SHM_SHARED,
|
|
|
- B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
|
|
|
- }
|
|
|
-
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, false);
|
|
|
-}
|
|
|
-
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
|
|
|
-static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
|
|
|
- u8 *events, u8 *delays, u8 length)
|
|
|
-{
|
|
|
- struct b43_phy_n *nphy = dev->phy.n;
|
|
|
- u8 i;
|
|
|
- u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
|
|
|
- u16 offset1 = cmd << 4;
|
|
|
- u16 offset2 = offset1 + 0x80;
|
|
|
-
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, true);
|
|
|
-
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
|
|
|
-
|
|
|
- for (i = length; i < 16; i++) {
|
|
|
- b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
|
|
|
- b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
|
|
|
- }
|
|
|
-
|
|
|
- if (nphy->hang_avoid)
|
|
|
- b43_nphy_stay_in_carrier_search(dev, false);
|
|
|
-}
|
|
|
-
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
|
|
|
-static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
|
|
|
- enum b43_nphy_rf_sequence seq)
|
|
|
-{
|
|
|
- static const u16 trigger[] = {
|
|
|
- [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
|
|
|
- [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
|
|
|
- [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
|
|
|
- [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
|
|
|
- [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
|
|
|
- [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
|
|
|
- };
|
|
|
- int i;
|
|
|
- u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
|
|
|
-
|
|
|
- B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
|
|
|
-
|
|
|
- b43_phy_set(dev, B43_NPHY_RFSEQMODE,
|
|
|
- B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
|
|
|
- b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
|
|
|
- for (i = 0; i < 200; i++) {
|
|
|
- if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
|
|
|
- goto ok;
|
|
|
- msleep(1);
|
|
|
+ /*
|
|
|
+ for (i = 0; i < 2; i++) {
|
|
|
+ nphy->txpwrindex[i].index_internal = txpi[i];
|
|
|
+ nphy->txpwrindex[i].index_internal_save = txpi[i];
|
|
|
}
|
|
|
- b43err(dev->wl, "RF sequence status timeout\n");
|
|
|
-ok:
|
|
|
- b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
|
|
|
-}
|
|
|
-
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
|
|
|
-static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
|
|
|
- u16 value, u8 core, bool off)
|
|
|
-{
|
|
|
- int i;
|
|
|
- u8 index = fls(field);
|
|
|
- u8 addr, en_addr, val_addr;
|
|
|
- /* we expect only one bit set */
|
|
|
- B43_WARN_ON(field & (~(1 << (index - 1))));
|
|
|
-
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- const struct nphy_rf_control_override_rev3 *rf_ctrl;
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- if (index == 0 || index == 16) {
|
|
|
- b43err(dev->wl,
|
|
|
- "Unsupported RF Ctrl Override call\n");
|
|
|
- return;
|
|
|
- }
|
|
|
-
|
|
|
- rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
|
|
|
- en_addr = B43_PHY_N((i == 0) ?
|
|
|
- rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
|
|
|
- val_addr = B43_PHY_N((i == 0) ?
|
|
|
- rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
|
|
|
+ */
|
|
|
|
|
|
- if (off) {
|
|
|
- b43_phy_mask(dev, en_addr, ~(field));
|
|
|
- b43_phy_mask(dev, val_addr,
|
|
|
- ~(rf_ctrl->val_mask));
|
|
|
+ for (i = 0; i < 2; i++) {
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ if (b43_nphy_ipa(dev)) {
|
|
|
+ txgain = *(b43_nphy_get_ipa_gain_table(dev) +
|
|
|
+ txpi[i]);
|
|
|
+ } else if (b43_current_band(dev->wl) ==
|
|
|
+ IEEE80211_BAND_5GHZ) {
|
|
|
+ /* FIXME: use 5GHz tables */
|
|
|
+ txgain =
|
|
|
+ b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
|
|
|
} else {
|
|
|
- if (core == 0 || ((1 << core) & i) != 0) {
|
|
|
- b43_phy_set(dev, en_addr, field);
|
|
|
- b43_phy_maskset(dev, val_addr,
|
|
|
- ~(rf_ctrl->val_mask),
|
|
|
- (value << rf_ctrl->val_shift));
|
|
|
- }
|
|
|
+ if (dev->phy.rev >= 5 &&
|
|
|
+ sprom->fem.ghz5.extpa_gain == 3)
|
|
|
+ ; /* FIXME: 5GHz_txgain_HiPwrEPA */
|
|
|
+ txgain =
|
|
|
+ b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
|
|
|
}
|
|
|
- }
|
|
|
- } else {
|
|
|
- const struct nphy_rf_control_override_rev2 *rf_ctrl;
|
|
|
- if (off) {
|
|
|
- b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
|
|
|
- value = 0;
|
|
|
+ radio_gain = (txgain >> 16) & 0x1FFFF;
|
|
|
} else {
|
|
|
- b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
|
|
|
+ txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
|
|
|
+ radio_gain = (txgain >> 16) & 0x1FFF;
|
|
|
}
|
|
|
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- if (index <= 1 || index == 16) {
|
|
|
- b43err(dev->wl,
|
|
|
- "Unsupported RF Ctrl Override call\n");
|
|
|
- return;
|
|
|
- }
|
|
|
+ if (dev->phy.rev >= 7)
|
|
|
+ dac_gain = (txgain >> 8) & 0x7;
|
|
|
+ else
|
|
|
+ dac_gain = (txgain >> 8) & 0x3F;
|
|
|
+ bbmult = txgain & 0xFF;
|
|
|
|
|
|
- if (index == 2 || index == 10 ||
|
|
|
- (index >= 13 && index <= 15)) {
|
|
|
- core = 1;
|
|
|
- }
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ if (i == 0)
|
|
|
+ b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
|
|
|
+ else
|
|
|
+ b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
|
|
|
+ } else {
|
|
|
+ b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
|
|
|
+ }
|
|
|
|
|
|
- rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
|
|
|
- addr = B43_PHY_N((i == 0) ?
|
|
|
- rf_ctrl->addr0 : rf_ctrl->addr1);
|
|
|
+ if (i == 0)
|
|
|
+ b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
|
|
|
+ else
|
|
|
+ b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
|
|
|
|
|
|
- if ((core & (1 << i)) != 0)
|
|
|
- b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
|
|
|
- (value << rf_ctrl->shift));
|
|
|
+ b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
|
|
|
|
|
|
- b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
|
|
|
- b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
|
|
- B43_NPHY_RFCTL_CMD_START);
|
|
|
- udelay(1);
|
|
|
- b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
|
|
|
+ tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
|
|
|
+ if (i == 0)
|
|
|
+ tmp = (tmp & 0x00FF) | (bbmult << 8);
|
|
|
+ else
|
|
|
+ tmp = (tmp & 0xFF00) | bbmult;
|
|
|
+ b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
|
|
|
+
|
|
|
+ if (b43_nphy_ipa(dev)) {
|
|
|
+ u32 tmp32;
|
|
|
+ u16 reg = (i == 0) ?
|
|
|
+ B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
|
|
|
+ tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
|
|
|
+ 576 + txpi[i]));
|
|
|
+ b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
|
|
|
+ b43_phy_set(dev, reg, 0x4);
|
|
|
}
|
|
|
}
|
|
|
-}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
|
|
|
-static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
|
|
|
- u16 value, u8 core)
|
|
|
-{
|
|
|
- u8 i, j;
|
|
|
- u16 reg, tmp, val;
|
|
|
-
|
|
|
- B43_WARN_ON(dev->phy.rev < 3);
|
|
|
- B43_WARN_ON(field > 4);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
|
|
|
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- if ((core == 1 && i == 1) || (core == 2 && !i))
|
|
|
- continue;
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, 0);
|
|
|
+}
|
|
|
|
|
|
- reg = (i == 0) ?
|
|
|
- B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
|
|
|
- b43_phy_mask(dev, reg, 0xFBFF);
|
|
|
+static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ struct b43_phy *phy = &dev->phy;
|
|
|
|
|
|
- switch (field) {
|
|
|
- case 0:
|
|
|
- b43_phy_write(dev, reg, 0);
|
|
|
- b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
|
|
|
- break;
|
|
|
- case 1:
|
|
|
- if (!i) {
|
|
|
- b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
|
|
|
- 0xFC3F, (value << 6));
|
|
|
- b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
|
|
|
- 0xFFFE, 1);
|
|
|
- b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
|
|
- B43_NPHY_RFCTL_CMD_START);
|
|
|
- for (j = 0; j < 100; j++) {
|
|
|
- if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
|
|
|
- j = 0;
|
|
|
- break;
|
|
|
- }
|
|
|
- udelay(10);
|
|
|
- }
|
|
|
- if (j)
|
|
|
- b43err(dev->wl,
|
|
|
- "intc override timeout\n");
|
|
|
- b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
|
|
|
- 0xFFFE);
|
|
|
- } else {
|
|
|
- b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
|
|
|
- 0xFC3F, (value << 6));
|
|
|
- b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
|
|
|
- 0xFFFE, 1);
|
|
|
- b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
|
|
- B43_NPHY_RFCTL_CMD_RXTX);
|
|
|
- for (j = 0; j < 100; j++) {
|
|
|
- if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
|
|
|
- j = 0;
|
|
|
- break;
|
|
|
- }
|
|
|
- udelay(10);
|
|
|
- }
|
|
|
- if (j)
|
|
|
- b43err(dev->wl,
|
|
|
- "intc override timeout\n");
|
|
|
- b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
|
|
|
- 0xFFFE);
|
|
|
- }
|
|
|
- break;
|
|
|
- case 2:
|
|
|
- if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
|
|
|
- tmp = 0x0020;
|
|
|
- val = value << 5;
|
|
|
- } else {
|
|
|
- tmp = 0x0010;
|
|
|
- val = value << 4;
|
|
|
- }
|
|
|
- b43_phy_maskset(dev, reg, ~tmp, val);
|
|
|
- break;
|
|
|
- case 3:
|
|
|
- if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
|
|
|
- tmp = 0x0001;
|
|
|
- val = value;
|
|
|
- } else {
|
|
|
- tmp = 0x0004;
|
|
|
- val = value << 2;
|
|
|
- }
|
|
|
- b43_phy_maskset(dev, reg, ~tmp, val);
|
|
|
- break;
|
|
|
- case 4:
|
|
|
+ const u32 *table = NULL;
|
|
|
+#if 0
|
|
|
+ TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
|
|
|
+ u32 rfpwr_offset;
|
|
|
+ u8 pga_gain;
|
|
|
+ int i;
|
|
|
+#endif
|
|
|
+
|
|
|
+ if (phy->rev >= 3) {
|
|
|
+ if (b43_nphy_ipa(dev)) {
|
|
|
+ table = b43_nphy_get_ipa_gain_table(dev);
|
|
|
+ } else {
|
|
|
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
|
|
|
- tmp = 0x0002;
|
|
|
- val = value << 1;
|
|
|
+ if (phy->rev == 3)
|
|
|
+ table = b43_ntab_tx_gain_rev3_5ghz;
|
|
|
+ if (phy->rev == 4)
|
|
|
+ table = b43_ntab_tx_gain_rev4_5ghz;
|
|
|
+ else
|
|
|
+ table = b43_ntab_tx_gain_rev5plus_5ghz;
|
|
|
} else {
|
|
|
- tmp = 0x0008;
|
|
|
- val = value << 3;
|
|
|
+ table = b43_ntab_tx_gain_rev3plus_2ghz;
|
|
|
}
|
|
|
- b43_phy_maskset(dev, reg, ~tmp, val);
|
|
|
- break;
|
|
|
}
|
|
|
+ } else {
|
|
|
+ table = b43_ntab_tx_gain_rev0_1_2;
|
|
|
+ }
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
|
|
|
+
|
|
|
+ if (phy->rev >= 3) {
|
|
|
+#if 0
|
|
|
+ nphy->gmval = (table[0] >> 16) & 0x7000;
|
|
|
+
|
|
|
+ for (i = 0; i < 128; i++) {
|
|
|
+ pga_gain = (table[i] >> 24) & 0xF;
|
|
|
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
|
|
|
+ rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
|
|
|
+ else
|
|
|
+ rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
|
|
|
+ b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
|
|
|
+ rfpwr_offset);
|
|
|
+ b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
|
|
|
+ rfpwr_offset);
|
|
|
+ }
|
|
|
+#endif
|
|
|
}
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
|
|
|
-static void b43_nphy_bphy_init(struct b43_wldev *dev)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
|
|
|
+static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
|
|
|
{
|
|
|
- unsigned int i;
|
|
|
- u16 val;
|
|
|
+ struct b43_phy_n *nphy = dev->phy.n;
|
|
|
+ enum ieee80211_band band;
|
|
|
+ u16 tmp;
|
|
|
|
|
|
- val = 0x1E1F;
|
|
|
- for (i = 0; i < 16; i++) {
|
|
|
- b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
|
|
|
- val -= 0x202;
|
|
|
- }
|
|
|
- val = 0x3E3F;
|
|
|
- for (i = 0; i < 16; i++) {
|
|
|
- b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
|
|
|
- val -= 0x202;
|
|
|
+ if (!enable) {
|
|
|
+ nphy->rfctrl_intc1_save = b43_phy_read(dev,
|
|
|
+ B43_NPHY_RFCTL_INTC1);
|
|
|
+ nphy->rfctrl_intc2_save = b43_phy_read(dev,
|
|
|
+ B43_NPHY_RFCTL_INTC2);
|
|
|
+ band = b43_current_band(dev->wl);
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ if (band == IEEE80211_BAND_5GHZ)
|
|
|
+ tmp = 0x600;
|
|
|
+ else
|
|
|
+ tmp = 0x480;
|
|
|
+ } else {
|
|
|
+ if (band == IEEE80211_BAND_5GHZ)
|
|
|
+ tmp = 0x180;
|
|
|
+ else
|
|
|
+ tmp = 0x120;
|
|
|
+ }
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
|
|
|
+ } else {
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
|
|
|
+ nphy->rfctrl_intc1_save);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
|
|
|
+ nphy->rfctrl_intc2_save);
|
|
|
}
|
|
|
- b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
|
|
|
-static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
|
|
|
- s8 offset, u8 core, u8 rail,
|
|
|
- enum b43_nphy_rssi_type type)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
|
|
|
+static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
|
|
|
{
|
|
|
u16 tmp;
|
|
|
- bool core1or5 = (core == 1) || (core == 5);
|
|
|
- bool core2or5 = (core == 2) || (core == 5);
|
|
|
-
|
|
|
- offset = clamp_val(offset, -32, 31);
|
|
|
- tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
|
|
|
|
|
|
- if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
|
|
|
- if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
|
|
|
- if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
|
|
|
- if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ if (b43_nphy_ipa(dev)) {
|
|
|
+ tmp = 4;
|
|
|
+ b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
|
|
|
+ (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
|
|
|
+ }
|
|
|
|
|
|
- if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
|
|
|
- if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
|
|
|
- if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
|
|
|
- if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
|
|
|
+ tmp = 1;
|
|
|
+ b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
|
|
|
+ (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
|
|
|
+ }
|
|
|
+}
|
|
|
|
|
|
- if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
|
|
|
- if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
|
|
|
- if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
|
|
|
- if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
|
|
|
+static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ struct b43_phy_n *nphy = dev->phy.n;
|
|
|
|
|
|
- if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
|
|
|
- if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
|
|
|
- if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
|
|
|
- if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
|
|
|
+ bool override = false;
|
|
|
+ u16 chain = 0x33;
|
|
|
|
|
|
- if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
|
|
|
- if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
|
|
|
- if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
|
|
|
- if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
|
|
|
+ if (nphy->txrx_chain == 0) {
|
|
|
+ chain = 0x11;
|
|
|
+ override = true;
|
|
|
+ } else if (nphy->txrx_chain == 1) {
|
|
|
+ chain = 0x22;
|
|
|
+ override = true;
|
|
|
+ }
|
|
|
|
|
|
- if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
|
|
|
- if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
|
|
|
+ ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
|
|
|
+ chain);
|
|
|
|
|
|
- if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
|
|
|
- if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
|
|
|
- b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
|
|
|
+ if (override)
|
|
|
+ b43_phy_set(dev, B43_NPHY_RFSEQMODE,
|
|
|
+ B43_NPHY_RFSEQMODE_CAOVER);
|
|
|
+ else
|
|
|
+ b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
|
|
|
+ ~B43_NPHY_RFSEQMODE_CAOVER);
|
|
|
}
|
|
|
|
|
|
-static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
|
|
|
+static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
|
|
|
+ u16 samps, u8 time, bool wait)
|
|
|
{
|
|
|
- u16 val;
|
|
|
+ int i;
|
|
|
+ u16 tmp;
|
|
|
|
|
|
- if (type < 3)
|
|
|
- val = 0;
|
|
|
- else if (type == 6)
|
|
|
- val = 1;
|
|
|
- else if (type == 3)
|
|
|
- val = 2;
|
|
|
+ b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
|
|
|
+ if (wait)
|
|
|
+ b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
|
|
|
else
|
|
|
- val = 3;
|
|
|
+ b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
|
|
|
|
|
|
- val = (val << 12) | (val << 14);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
|
|
|
+ b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
|
|
|
|
|
|
- if (type < 3) {
|
|
|
- b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
|
|
|
- (type + 1) << 4);
|
|
|
- b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
|
|
|
- (type + 1) << 4);
|
|
|
- }
|
|
|
+ for (i = 1000; i; i--) {
|
|
|
+ tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
|
|
|
+ if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
|
|
|
+ est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
|
|
|
+ b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
|
|
|
+ est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
|
|
|
+ b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
|
|
|
+ est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
|
|
|
+ b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
|
|
|
|
|
|
- if (code == 0) {
|
|
|
- b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
|
|
|
- if (type < 3) {
|
|
|
- b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
|
|
|
- ~(B43_NPHY_RFCTL_CMD_RXEN |
|
|
|
- B43_NPHY_RFCTL_CMD_CORESEL));
|
|
|
- b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
|
|
|
- ~(0x1 << 12 |
|
|
|
- 0x1 << 5 |
|
|
|
- 0x1 << 1 |
|
|
|
- 0x1));
|
|
|
- b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
|
|
|
- ~B43_NPHY_RFCTL_CMD_START);
|
|
|
- udelay(20);
|
|
|
- b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
|
|
|
- }
|
|
|
- } else {
|
|
|
- b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
|
|
|
- if (type < 3) {
|
|
|
- b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
|
|
|
- ~(B43_NPHY_RFCTL_CMD_RXEN |
|
|
|
- B43_NPHY_RFCTL_CMD_CORESEL),
|
|
|
- (B43_NPHY_RFCTL_CMD_RXEN |
|
|
|
- code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
|
|
|
- b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
|
|
|
- (0x1 << 12 |
|
|
|
- 0x1 << 5 |
|
|
|
- 0x1 << 1 |
|
|
|
- 0x1));
|
|
|
- b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
|
|
- B43_NPHY_RFCTL_CMD_START);
|
|
|
- udelay(20);
|
|
|
- b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
|
|
|
+ est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
|
|
|
+ b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
|
|
|
+ est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
|
|
|
+ b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
|
|
|
+ est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
|
|
|
+ b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
|
|
|
+ return;
|
|
|
}
|
|
|
+ udelay(10);
|
|
|
}
|
|
|
+ memset(est, 0, sizeof(*est));
|
|
|
}
|
|
|
|
|
|
-static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
|
|
|
+static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
|
|
|
+ struct b43_phy_n_iq_comp *pcomp)
|
|
|
{
|
|
|
- u8 i;
|
|
|
- u16 reg, val;
|
|
|
-
|
|
|
- if (code == 0) {
|
|
|
- b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
|
|
|
- b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
|
|
|
- b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
|
|
|
- b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
|
|
|
- b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
|
|
|
- b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
|
|
|
- b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
|
|
|
- b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
|
|
|
+ if (write) {
|
|
|
+ b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
|
|
|
+ b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
|
|
|
+ b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
|
|
|
+ b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
|
|
|
} else {
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- if ((code == 1 && i == 1) || (code == 2 && !i))
|
|
|
- continue;
|
|
|
-
|
|
|
- reg = (i == 0) ?
|
|
|
- B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
|
|
|
- b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
|
|
|
+ pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
|
|
|
+ pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
|
|
|
+ pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
|
|
|
+ pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
|
|
|
+ }
|
|
|
+}
|
|
|
|
|
|
- if (type < 3) {
|
|
|
- reg = (i == 0) ?
|
|
|
- B43_NPHY_AFECTL_C1 :
|
|
|
- B43_NPHY_AFECTL_C2;
|
|
|
- b43_phy_maskset(dev, reg, 0xFCFF, 0);
|
|
|
+#if 0
|
|
|
+/* Ready but not used anywhere */
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
|
|
|
+static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
|
|
|
+{
|
|
|
+ u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
|
|
|
|
|
|
- reg = (i == 0) ?
|
|
|
- B43_NPHY_RFCTL_LUT_TRSW_UP1 :
|
|
|
- B43_NPHY_RFCTL_LUT_TRSW_UP2;
|
|
|
- b43_phy_maskset(dev, reg, 0xFFC3, 0);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
|
|
|
+ if (core == 0) {
|
|
|
+ b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
|
|
|
+ } else {
|
|
|
+ b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
|
|
|
+ }
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
|
|
|
+ b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
|
|
|
+}
|
|
|
|
|
|
- if (type == 0)
|
|
|
- val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
|
|
|
- else if (type == 1)
|
|
|
- val = 16;
|
|
|
- else
|
|
|
- val = 32;
|
|
|
- b43_phy_set(dev, reg, val);
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
|
|
|
+static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
|
|
|
+{
|
|
|
+ u8 rxval, txval;
|
|
|
+ u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
|
|
|
|
|
|
- reg = (i == 0) ?
|
|
|
- B43_NPHY_TXF_40CO_B1S0 :
|
|
|
- B43_NPHY_TXF_40CO_B32S1;
|
|
|
- b43_phy_set(dev, reg, 0x0020);
|
|
|
- } else {
|
|
|
- if (type == 6)
|
|
|
- val = 0x0100;
|
|
|
- else if (type == 3)
|
|
|
- val = 0x0200;
|
|
|
- else
|
|
|
- val = 0x0300;
|
|
|
+ regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
|
|
|
+ if (core == 0) {
|
|
|
+ regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
|
|
|
+ regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
|
|
|
+ } else {
|
|
|
+ regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
|
|
|
+ regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
|
|
|
+ }
|
|
|
+ regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
|
|
|
+ regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
|
|
|
+ regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
|
|
|
+ regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
|
|
|
+ regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
|
|
|
+ regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
|
|
|
+ regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
|
|
|
+ regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
|
|
|
|
|
|
- reg = (i == 0) ?
|
|
|
- B43_NPHY_AFECTL_C1 :
|
|
|
- B43_NPHY_AFECTL_C2;
|
|
|
+ b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
|
|
|
+ b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
|
|
|
|
|
|
- b43_phy_maskset(dev, reg, 0xFCFF, val);
|
|
|
- b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
|
|
|
+ ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
|
|
|
+ ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
|
|
|
+ ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
|
|
|
+ (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
|
|
|
+ b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
|
|
|
+ (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
|
|
|
|
|
|
- if (type != 3 && type != 6) {
|
|
|
- enum ieee80211_band band =
|
|
|
- b43_current_band(dev->wl);
|
|
|
+ if (core == 0) {
|
|
|
+ b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
|
|
|
+ b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
|
|
|
+ } else {
|
|
|
+ b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
|
|
|
+ b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
|
|
|
+ }
|
|
|
|
|
|
- if (b43_nphy_ipa(dev))
|
|
|
- val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
|
|
|
- else
|
|
|
- val = 0x11;
|
|
|
- reg = (i == 0) ? 0x2000 : 0x3000;
|
|
|
- reg |= B2055_PADDRV;
|
|
|
- b43_radio_write16(dev, reg, val);
|
|
|
+ b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
|
|
|
+ b43_nphy_rf_control_override(dev, 8, 0, 3, false);
|
|
|
+ b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
|
|
|
|
|
|
- reg = (i == 0) ?
|
|
|
- B43_NPHY_AFECTL_OVER1 :
|
|
|
- B43_NPHY_AFECTL_OVER;
|
|
|
- b43_phy_set(dev, reg, 0x0200);
|
|
|
- }
|
|
|
- }
|
|
|
- }
|
|
|
+ if (core == 0) {
|
|
|
+ rxval = 1;
|
|
|
+ txval = 8;
|
|
|
+ } else {
|
|
|
+ rxval = 4;
|
|
|
+ txval = 2;
|
|
|
}
|
|
|
+ b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
|
|
|
+ b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
|
|
|
}
|
|
|
+#endif
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
|
|
|
-static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
|
|
|
-{
|
|
|
- if (dev->phy.rev >= 3)
|
|
|
- b43_nphy_rev3_rssi_select(dev, code, type);
|
|
|
- else
|
|
|
- b43_nphy_rev2_rssi_select(dev, code, type);
|
|
|
-}
|
|
|
-
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
|
|
|
-static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
|
|
|
+static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
|
|
|
{
|
|
|
int i;
|
|
|
+ s32 iq;
|
|
|
+ u32 ii;
|
|
|
+ u32 qq;
|
|
|
+ int iq_nbits, qq_nbits;
|
|
|
+ int arsh, brsh;
|
|
|
+ u16 tmp, a, b;
|
|
|
+
|
|
|
+ struct nphy_iq_est est;
|
|
|
+ struct b43_phy_n_iq_comp old;
|
|
|
+ struct b43_phy_n_iq_comp new = { };
|
|
|
+ bool error = false;
|
|
|
+
|
|
|
+ if (mask == 0)
|
|
|
+ return;
|
|
|
+
|
|
|
+ b43_nphy_rx_iq_coeffs(dev, false, &old);
|
|
|
+ b43_nphy_rx_iq_coeffs(dev, true, &new);
|
|
|
+ b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
|
|
|
+ new = old;
|
|
|
+
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
- if (type == 2) {
|
|
|
- if (i == 0) {
|
|
|
- b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
|
|
|
- 0xFC, buf[0]);
|
|
|
- b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
|
|
|
- 0xFC, buf[1]);
|
|
|
- } else {
|
|
|
- b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
|
|
|
- 0xFC, buf[2 * i]);
|
|
|
- b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
|
|
|
- 0xFC, buf[2 * i + 1]);
|
|
|
- }
|
|
|
+ if (i == 0 && (mask & 1)) {
|
|
|
+ iq = est.iq0_prod;
|
|
|
+ ii = est.i0_pwr;
|
|
|
+ qq = est.q0_pwr;
|
|
|
+ } else if (i == 1 && (mask & 2)) {
|
|
|
+ iq = est.iq1_prod;
|
|
|
+ ii = est.i1_pwr;
|
|
|
+ qq = est.q1_pwr;
|
|
|
} else {
|
|
|
- if (i == 0)
|
|
|
- b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
|
|
|
- 0xF3, buf[0] << 2);
|
|
|
- else
|
|
|
- b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
|
|
|
- 0xF3, buf[2 * i + 1] << 2);
|
|
|
+ continue;
|
|
|
}
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
|
|
|
-static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
|
|
|
- u8 nsamp)
|
|
|
-{
|
|
|
- int i;
|
|
|
- int out;
|
|
|
- u16 save_regs_phy[9];
|
|
|
- u16 s[2];
|
|
|
-
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- save_regs_phy[0] = b43_phy_read(dev,
|
|
|
- B43_NPHY_RFCTL_LUT_TRSW_UP1);
|
|
|
- save_regs_phy[1] = b43_phy_read(dev,
|
|
|
- B43_NPHY_RFCTL_LUT_TRSW_UP2);
|
|
|
- save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
|
|
|
- save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
|
|
|
- save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
|
|
|
- save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
|
|
|
- save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
|
|
|
- save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
|
|
|
- save_regs_phy[8] = 0;
|
|
|
- } else {
|
|
|
- save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
|
|
|
- save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
|
|
|
- save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
|
|
|
- save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
|
|
|
- save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
|
|
|
- save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
|
|
|
- save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
|
|
|
- save_regs_phy[7] = 0;
|
|
|
- save_regs_phy[8] = 0;
|
|
|
- }
|
|
|
|
|
|
- b43_nphy_rssi_select(dev, 5, type);
|
|
|
+ if (ii + qq < 2) {
|
|
|
+ error = true;
|
|
|
+ break;
|
|
|
+ }
|
|
|
|
|
|
- if (dev->phy.rev < 2) {
|
|
|
- save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
|
|
|
- b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
|
|
|
- }
|
|
|
+ iq_nbits = fls(abs(iq));
|
|
|
+ qq_nbits = fls(qq);
|
|
|
|
|
|
- for (i = 0; i < 4; i++)
|
|
|
- buf[i] = 0;
|
|
|
+ arsh = iq_nbits - 20;
|
|
|
+ if (arsh >= 0) {
|
|
|
+ a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
|
|
|
+ tmp = ii >> arsh;
|
|
|
+ } else {
|
|
|
+ a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
|
|
|
+ tmp = ii << -arsh;
|
|
|
+ }
|
|
|
+ if (tmp == 0) {
|
|
|
+ error = true;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ a /= tmp;
|
|
|
|
|
|
- for (i = 0; i < nsamp; i++) {
|
|
|
- if (dev->phy.rev < 2) {
|
|
|
- s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
|
|
|
- s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
|
|
|
+ brsh = qq_nbits - 11;
|
|
|
+ if (brsh >= 0) {
|
|
|
+ b = (qq << (31 - qq_nbits));
|
|
|
+ tmp = ii >> brsh;
|
|
|
} else {
|
|
|
- s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
|
|
|
- s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
|
|
|
+ b = (qq << (31 - qq_nbits));
|
|
|
+ tmp = ii << -brsh;
|
|
|
+ }
|
|
|
+ if (tmp == 0) {
|
|
|
+ error = true;
|
|
|
+ break;
|
|
|
}
|
|
|
+ b = int_sqrt(b / tmp - a * a) - (1 << 10);
|
|
|
|
|
|
- buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
|
|
|
- buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
|
|
|
- buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
|
|
|
- buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
|
|
|
+ if (i == 0 && (mask & 0x1)) {
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ new.a0 = a & 0x3FF;
|
|
|
+ new.b0 = b & 0x3FF;
|
|
|
+ } else {
|
|
|
+ new.a0 = b & 0x3FF;
|
|
|
+ new.b0 = a & 0x3FF;
|
|
|
+ }
|
|
|
+ } else if (i == 1 && (mask & 0x2)) {
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ new.a1 = a & 0x3FF;
|
|
|
+ new.b1 = b & 0x3FF;
|
|
|
+ } else {
|
|
|
+ new.a1 = b & 0x3FF;
|
|
|
+ new.b1 = a & 0x3FF;
|
|
|
+ }
|
|
|
+ }
|
|
|
}
|
|
|
- out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
|
|
|
- (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
|
|
|
|
|
|
- if (dev->phy.rev < 2)
|
|
|
- b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
|
|
|
+ if (error)
|
|
|
+ new = old;
|
|
|
|
|
|
- if (dev->phy.rev >= 3) {
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
|
|
|
- save_regs_phy[0]);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
|
|
|
- save_regs_phy[1]);
|
|
|
- b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
|
|
|
- b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
|
|
|
- b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
|
|
|
- b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
|
|
|
- b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
|
|
|
- b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
|
|
|
- } else {
|
|
|
- b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
|
|
|
- b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
|
|
|
- b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
|
|
|
- }
|
|
|
+ b43_nphy_rx_iq_coeffs(dev, true, &new);
|
|
|
+}
|
|
|
|
|
|
- return out;
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
|
|
|
+static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ u16 array[4];
|
|
|
+ b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
|
|
|
+
|
|
|
+ b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
|
|
|
+ b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
|
|
|
+ b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
|
|
|
+ b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
|
|
|
-static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
|
|
|
+static void b43_nphy_stop_playback(struct b43_wldev *dev)
|
|
|
{
|
|
|
- int i, j;
|
|
|
- u8 state[4];
|
|
|
- u8 code, val;
|
|
|
- u16 class, override;
|
|
|
- u8 regs_save_radio[2];
|
|
|
- u16 regs_save_phy[2];
|
|
|
+ struct b43_phy_n *nphy = dev->phy.n;
|
|
|
+ u16 tmp;
|
|
|
|
|
|
- s8 offset[4];
|
|
|
- u8 core;
|
|
|
- u8 rail;
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, 1);
|
|
|
|
|
|
- u16 clip_state[2];
|
|
|
- u16 clip_off[2] = { 0xFFFF, 0xFFFF };
|
|
|
- s32 results_min[4] = { };
|
|
|
- u8 vcm_final[4] = { };
|
|
|
- s32 results[4][4] = { };
|
|
|
- s32 miniq[4][2] = { };
|
|
|
+ tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
|
|
|
+ if (tmp & 0x1)
|
|
|
+ b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
|
|
|
+ else if (tmp & 0x2)
|
|
|
+ b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
|
|
|
|
|
|
- if (type == 2) {
|
|
|
- code = 0;
|
|
|
- val = 6;
|
|
|
- } else if (type < 2) {
|
|
|
- code = 25;
|
|
|
- val = 4;
|
|
|
- } else {
|
|
|
- B43_WARN_ON(1);
|
|
|
- return;
|
|
|
- }
|
|
|
+ b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
|
|
|
|
|
|
- class = b43_nphy_classifier(dev, 0, 0);
|
|
|
- b43_nphy_classifier(dev, 7, 4);
|
|
|
- b43_nphy_read_clip_detection(dev, clip_state);
|
|
|
- b43_nphy_write_clip_detection(dev, clip_off);
|
|
|
+ if (nphy->bb_mult_save & 0x80000000) {
|
|
|
+ tmp = nphy->bb_mult_save & 0xFFFF;
|
|
|
+ b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
|
|
|
+ nphy->bb_mult_save = 0;
|
|
|
+ }
|
|
|
|
|
|
- if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
|
|
|
- override = 0x140;
|
|
|
- else
|
|
|
- override = 0x110;
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, 0);
|
|
|
+}
|
|
|
|
|
|
- regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
|
|
|
- regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
|
|
|
- b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
|
|
|
+static void b43_nphy_spur_workaround(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ struct b43_phy_n *nphy = dev->phy.n;
|
|
|
|
|
|
- regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
|
|
|
- regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
|
|
|
- b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
|
|
|
+ u8 channel = dev->phy.channel;
|
|
|
+ int tone[2] = { 57, 58 };
|
|
|
+ u32 noise[2] = { 0x3FF, 0x3FF };
|
|
|
|
|
|
- state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
|
|
|
- state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
|
|
|
- b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
|
|
|
- b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
|
|
|
- state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
|
|
|
- state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
|
|
|
+ B43_WARN_ON(dev->phy.rev < 3);
|
|
|
|
|
|
- b43_nphy_rssi_select(dev, 5, type);
|
|
|
- b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
|
|
|
- b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, 1);
|
|
|
|
|
|
- for (i = 0; i < 4; i++) {
|
|
|
- u8 tmp[4];
|
|
|
- for (j = 0; j < 4; j++)
|
|
|
- tmp[j] = i;
|
|
|
- if (type != 1)
|
|
|
- b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
|
|
|
- b43_nphy_poll_rssi(dev, type, results[i], 8);
|
|
|
- if (type < 2)
|
|
|
- for (j = 0; j < 2; j++)
|
|
|
- miniq[i][j] = min(results[i][2 * j],
|
|
|
- results[i][2 * j + 1]);
|
|
|
+ if (nphy->gband_spurwar_en) {
|
|
|
+ /* TODO: N PHY Adjust Analog Pfbw (7) */
|
|
|
+ if (channel == 11 && dev->phy.is_40mhz)
|
|
|
+ ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
|
|
|
+ else
|
|
|
+ ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
|
|
|
+ /* TODO: N PHY Adjust CRS Min Power (0x1E) */
|
|
|
}
|
|
|
|
|
|
- for (i = 0; i < 4; i++) {
|
|
|
- s32 mind = 40;
|
|
|
- u8 minvcm = 0;
|
|
|
- s32 minpoll = 249;
|
|
|
- s32 curr;
|
|
|
- for (j = 0; j < 4; j++) {
|
|
|
- if (type == 2)
|
|
|
- curr = abs(results[j][i]);
|
|
|
- else
|
|
|
- curr = abs(miniq[j][i / 2] - code * 8);
|
|
|
-
|
|
|
- if (curr < mind) {
|
|
|
- mind = curr;
|
|
|
- minvcm = j;
|
|
|
+ if (nphy->aband_spurwar_en) {
|
|
|
+ if (channel == 54) {
|
|
|
+ tone[0] = 0x20;
|
|
|
+ noise[0] = 0x25F;
|
|
|
+ } else if (channel == 38 || channel == 102 || channel == 118) {
|
|
|
+ if (0 /* FIXME */) {
|
|
|
+ tone[0] = 0x20;
|
|
|
+ noise[0] = 0x21F;
|
|
|
+ } else {
|
|
|
+ tone[0] = 0;
|
|
|
+ noise[0] = 0;
|
|
|
}
|
|
|
-
|
|
|
- if (results[j][i] < minpoll)
|
|
|
- minpoll = results[j][i];
|
|
|
+ } else if (channel == 134) {
|
|
|
+ tone[0] = 0x20;
|
|
|
+ noise[0] = 0x21F;
|
|
|
+ } else if (channel == 151) {
|
|
|
+ tone[0] = 0x10;
|
|
|
+ noise[0] = 0x23F;
|
|
|
+ } else if (channel == 153 || channel == 161) {
|
|
|
+ tone[0] = 0x30;
|
|
|
+ noise[0] = 0x23F;
|
|
|
+ } else {
|
|
|
+ tone[0] = 0;
|
|
|
+ noise[0] = 0;
|
|
|
}
|
|
|
- results_min[i] = minpoll;
|
|
|
- vcm_final[i] = minvcm;
|
|
|
- }
|
|
|
-
|
|
|
- if (type != 1)
|
|
|
- b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
|
|
|
|
|
|
- for (i = 0; i < 4; i++) {
|
|
|
- offset[i] = (code * 8) - results[vcm_final[i]][i];
|
|
|
-
|
|
|
- if (offset[i] < 0)
|
|
|
- offset[i] = -((abs(offset[i]) + 4) / 8);
|
|
|
+ if (!tone[0] && !noise[0])
|
|
|
+ ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
|
|
|
else
|
|
|
- offset[i] = (offset[i] + 4) / 8;
|
|
|
+ ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
|
|
|
+ }
|
|
|
|
|
|
- if (results_min[i] == 248)
|
|
|
- offset[i] = code - 32;
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, 0);
|
|
|
+}
|
|
|
|
|
|
- core = (i / 2) ? 2 : 1;
|
|
|
- rail = (i % 2) ? 1 : 0;
|
|
|
+/*
|
|
|
+ * Transmits a known value for LO calibration
|
|
|
+ * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
|
|
|
+ */
|
|
|
+static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
|
|
|
+ bool iqmode, bool dac_test)
|
|
|
+{
|
|
|
+ u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
|
|
|
+ if (samp == 0)
|
|
|
+ return -1;
|
|
|
+ b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
|
|
|
- b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
|
|
|
- type);
|
|
|
- }
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
|
|
|
+static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ struct b43_phy_n *nphy = dev->phy.n;
|
|
|
+ int i, j;
|
|
|
+ u32 tmp;
|
|
|
+ u32 cur_real, cur_imag, real_part, imag_part;
|
|
|
|
|
|
- b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
|
|
|
- b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
|
|
|
+ u16 buffer[7];
|
|
|
|
|
|
- switch (state[2]) {
|
|
|
- case 1:
|
|
|
- b43_nphy_rssi_select(dev, 1, 2);
|
|
|
- break;
|
|
|
- case 4:
|
|
|
- b43_nphy_rssi_select(dev, 1, 0);
|
|
|
- break;
|
|
|
- case 2:
|
|
|
- b43_nphy_rssi_select(dev, 1, 1);
|
|
|
- break;
|
|
|
- default:
|
|
|
- b43_nphy_rssi_select(dev, 1, 1);
|
|
|
- break;
|
|
|
- }
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, true);
|
|
|
|
|
|
- switch (state[3]) {
|
|
|
- case 1:
|
|
|
- b43_nphy_rssi_select(dev, 2, 2);
|
|
|
- break;
|
|
|
- case 4:
|
|
|
- b43_nphy_rssi_select(dev, 2, 0);
|
|
|
- break;
|
|
|
- default:
|
|
|
- b43_nphy_rssi_select(dev, 2, 1);
|
|
|
- break;
|
|
|
- }
|
|
|
+ b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
|
|
|
|
|
|
- b43_nphy_rssi_select(dev, 0, type);
|
|
|
+ for (i = 0; i < 2; i++) {
|
|
|
+ tmp = ((buffer[i * 2] & 0x3FF) << 10) |
|
|
|
+ (buffer[i * 2 + 1] & 0x3FF);
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
|
|
|
+ (((i + 26) << 10) | 320));
|
|
|
+ for (j = 0; j < 128; j++) {
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
|
|
|
+ ((tmp >> 16) & 0xFFFF));
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
|
|
|
+ (tmp & 0xFFFF));
|
|
|
+ }
|
|
|
+ }
|
|
|
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
|
|
|
- b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
|
|
|
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
|
|
|
- b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
|
|
|
+ for (i = 0; i < 2; i++) {
|
|
|
+ tmp = buffer[5 + i];
|
|
|
+ real_part = (tmp >> 8) & 0xFF;
|
|
|
+ imag_part = (tmp & 0xFF);
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
|
|
|
+ (((i + 26) << 10) | 448));
|
|
|
|
|
|
- b43_nphy_classifier(dev, 7, class);
|
|
|
- b43_nphy_write_clip_detection(dev, clip_state);
|
|
|
- /* Specs don't say about reset here, but it makes wl and b43 dumps
|
|
|
- identical, it really seems wl performs this */
|
|
|
- b43_nphy_reset_cca(dev);
|
|
|
-}
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ cur_real = real_part;
|
|
|
+ cur_imag = imag_part;
|
|
|
+ tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
|
|
|
+ }
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
|
|
|
-static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
|
|
|
-{
|
|
|
- /* TODO */
|
|
|
-}
|
|
|
+ for (j = 0; j < 128; j++) {
|
|
|
+ if (dev->phy.rev < 3) {
|
|
|
+ cur_real = (real_part * loscale[j] + 128) >> 8;
|
|
|
+ cur_imag = (imag_part * loscale[j] + 128) >> 8;
|
|
|
+ tmp = ((cur_real & 0xFF) << 8) |
|
|
|
+ (cur_imag & 0xFF);
|
|
|
+ }
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
|
|
|
+ ((tmp >> 16) & 0xFFFF));
|
|
|
+ b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
|
|
|
+ (tmp & 0xFFFF));
|
|
|
+ }
|
|
|
+ }
|
|
|
|
|
|
-/*
|
|
|
- * RSSI Calibration
|
|
|
- * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
|
|
|
- */
|
|
|
-static void b43_nphy_rssi_cal(struct b43_wldev *dev)
|
|
|
-{
|
|
|
if (dev->phy.rev >= 3) {
|
|
|
- b43_nphy_rev3_rssi_cal(dev);
|
|
|
- } else {
|
|
|
- b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
|
|
|
- b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
|
|
|
- b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
|
|
|
+ b43_shm_write16(dev, B43_SHM_SHARED,
|
|
|
+ B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
|
|
|
+ b43_shm_write16(dev, B43_SHM_SHARED,
|
|
|
+ B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
|
|
|
}
|
|
|
+
|
|
|
+ if (nphy->hang_avoid)
|
|
|
+ b43_nphy_stay_in_carrier_search(dev, false);
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -2846,24 +2778,6 @@ static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
|
|
|
b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
|
|
|
}
|
|
|
|
|
|
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
|
|
|
-static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
|
|
|
-{
|
|
|
- if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
|
|
|
- if (dev->phy.rev >= 6) {
|
|
|
- if (dev->dev->chip_id == 47162)
|
|
|
- return txpwrctrl_tx_gain_ipa_rev5;
|
|
|
- return txpwrctrl_tx_gain_ipa_rev6;
|
|
|
- } else if (dev->phy.rev >= 5) {
|
|
|
- return txpwrctrl_tx_gain_ipa_rev5;
|
|
|
- } else {
|
|
|
- return txpwrctrl_tx_gain_ipa;
|
|
|
- }
|
|
|
- } else {
|
|
|
- return txpwrctrl_tx_gain_ipa_5g;
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
|
|
|
static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
|
|
|
{
|
|
@@ -3847,10 +3761,104 @@ static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
|
|
|
b43_mac_enable(dev);
|
|
|
}
|
|
|
|
|
|
+/**************************************************
|
|
|
+ * N-PHY init
|
|
|
+ **************************************************/
|
|
|
+
|
|
|
/*
|
|
|
- * Init N-PHY
|
|
|
- * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
|
|
|
+ * Upload the N-PHY tables.
|
|
|
+ * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
|
|
|
*/
|
|
|
+static void b43_nphy_tables_init(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ if (dev->phy.rev < 3)
|
|
|
+ b43_nphy_rev0_1_2_tables_init(dev);
|
|
|
+ else
|
|
|
+ b43_nphy_rev3plus_tables_init(dev);
|
|
|
+}
|
|
|
+
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
|
|
|
+static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
|
|
|
+{
|
|
|
+ u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
|
|
|
+
|
|
|
+ mimocfg |= B43_NPHY_MIMOCFG_AUTO;
|
|
|
+ if (preamble == 1)
|
|
|
+ mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
|
|
|
+ else
|
|
|
+ mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
|
|
|
+
|
|
|
+ b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
|
|
|
+}
|
|
|
+
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
|
|
|
+static void b43_nphy_bphy_init(struct b43_wldev *dev)
|
|
|
+{
|
|
|
+ unsigned int i;
|
|
|
+ u16 val;
|
|
|
+
|
|
|
+ val = 0x1E1F;
|
|
|
+ for (i = 0; i < 16; i++) {
|
|
|
+ b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
|
|
|
+ val -= 0x202;
|
|
|
+ }
|
|
|
+ val = 0x3E3F;
|
|
|
+ for (i = 0; i < 16; i++) {
|
|
|
+ b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
|
|
|
+ val -= 0x202;
|
|
|
+ }
|
|
|
+ b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
|
|
|
+}
|
|
|
+
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
|
|
|
+static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
|
|
|
+{
|
|
|
+ if (dev->phy.rev >= 3) {
|
|
|
+ if (!init)
|
|
|
+ return;
|
|
|
+ if (0 /* FIXME */) {
|
|
|
+ b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
|
|
|
+ b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
|
|
|
+ b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
|
|
|
+ b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
|
|
|
+ b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
|
|
|
+
|
|
|
+ switch (dev->dev->bus_type) {
|
|
|
+#ifdef CONFIG_B43_BCMA
|
|
|
+ case B43_BUS_BCMA:
|
|
|
+ bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
|
|
|
+ 0xFC00, 0xFC00);
|
|
|
+ break;
|
|
|
+#endif
|
|
|
+#ifdef CONFIG_B43_SSB
|
|
|
+ case B43_BUS_SSB:
|
|
|
+ ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
|
|
|
+ 0xFC00, 0xFC00);
|
|
|
+ break;
|
|
|
+#endif
|
|
|
+ }
|
|
|
+
|
|
|
+ b43_write32(dev, B43_MMIO_MACCTL,
|
|
|
+ b43_read32(dev, B43_MMIO_MACCTL) &
|
|
|
+ ~B43_MACCTL_GPOUTSMSK);
|
|
|
+ b43_write16(dev, B43_MMIO_GPIO_MASK,
|
|
|
+ b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
|
|
|
+ b43_write16(dev, B43_MMIO_GPIO_CONTROL,
|
|
|
+ b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
|
|
|
+
|
|
|
+ if (init) {
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
|
|
|
+ b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
|
|
|
int b43_phy_initn(struct b43_wldev *dev)
|
|
|
{
|
|
|
struct ssb_sprom *sprom = dev->dev->bus_sprom;
|
|
@@ -4045,11 +4053,26 @@ int b43_phy_initn(struct b43_wldev *dev)
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
+/**************************************************
|
|
|
+ * Channel switching ops.
|
|
|
+ **************************************************/
|
|
|
+
|
|
|
+static void b43_chantab_phy_upload(struct b43_wldev *dev,
|
|
|
+ const struct b43_phy_n_sfo_cfg *e)
|
|
|
+{
|
|
|
+ b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
|
|
|
+ b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
|
|
|
+ b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
|
|
|
+ b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
|
|
|
+ b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
|
|
|
+ b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
|
|
|
+}
|
|
|
+
|
|
|
/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
|
|
|
static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
|
|
|
{
|
|
|
- struct bcma_drv_cc *cc;
|
|
|
- u32 pmu_ctl;
|
|
|
+ struct bcma_drv_cc __maybe_unused *cc;
|
|
|
+ u32 __maybe_unused pmu_ctl;
|
|
|
|
|
|
switch (dev->dev->bus_type) {
|
|
|
#ifdef CONFIG_B43_BCMA
|
|
@@ -4260,6 +4283,10 @@ static int b43_nphy_set_channel(struct b43_wldev *dev,
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
+/**************************************************
|
|
|
+ * Basic PHY ops.
|
|
|
+ **************************************************/
|
|
|
+
|
|
|
static int b43_nphy_op_allocate(struct b43_wldev *dev)
|
|
|
{
|
|
|
struct b43_phy_n *nphy;
|