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@@ -445,8 +445,6 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
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s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
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{
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s32 status = 0;
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- u32 time_out;
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- u32 max_time_out = 10;
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u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
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bool autoneg = false;
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ixgbe_link_speed speed;
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@@ -514,25 +512,6 @@ s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
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hw->phy.ops.write_reg(hw, MDIO_CTRL1,
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MDIO_MMD_AN, autoneg_reg);
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- /* Wait for autonegotiation to finish */
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- for (time_out = 0; time_out < max_time_out; time_out++) {
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- udelay(10);
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- /* Restart PHY autonegotiation and wait for completion */
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- status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
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- MDIO_MMD_AN,
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- &autoneg_reg);
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-
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- autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
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- if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
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- break;
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- }
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- }
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-
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- if (time_out == max_time_out) {
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- hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out\n");
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- return IXGBE_ERR_LINK_SETUP;
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- }
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-
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return status;
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}
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@@ -657,8 +636,6 @@ s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
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s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
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{
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s32 status;
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- u32 time_out;
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- u32 max_time_out = 10;
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u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
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bool autoneg = false;
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ixgbe_link_speed speed;
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@@ -724,24 +701,6 @@ s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
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hw->phy.ops.write_reg(hw, MDIO_CTRL1,
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MDIO_MMD_AN, autoneg_reg);
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- /* Wait for autonegotiation to finish */
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- for (time_out = 0; time_out < max_time_out; time_out++) {
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- udelay(10);
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- /* Restart PHY autonegotiation and wait for completion */
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- status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
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- MDIO_MMD_AN,
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- &autoneg_reg);
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-
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- autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
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- if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
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- break;
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- }
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-
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- if (time_out == max_time_out) {
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- hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out\n");
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- return IXGBE_ERR_LINK_SETUP;
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- }
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-
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return status;
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}
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