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@@ -3071,7 +3071,7 @@ static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
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umr->flags = MLX5_UMR_INLINE;
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}
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-static __be64 get_umr_reg_mr_mask(void)
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+static __be64 get_umr_reg_mr_mask(int atomic)
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{
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u64 result;
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@@ -3084,9 +3084,11 @@ static __be64 get_umr_reg_mr_mask(void)
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MLX5_MKEY_MASK_KEY |
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MLX5_MKEY_MASK_RR |
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MLX5_MKEY_MASK_RW |
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- MLX5_MKEY_MASK_A |
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MLX5_MKEY_MASK_FREE;
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+ if (atomic)
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+ result |= MLX5_MKEY_MASK_A;
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+
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return cpu_to_be64(result);
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}
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@@ -3147,7 +3149,7 @@ static __be64 get_umr_update_pd_mask(void)
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}
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static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
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- struct ib_send_wr *wr)
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+ struct ib_send_wr *wr, int atomic)
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{
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struct mlx5_umr_wr *umrwr = umr_wr(wr);
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@@ -3172,7 +3174,7 @@ static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
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if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
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umr->mkey_mask |= get_umr_update_pd_mask();
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if (!umr->mkey_mask)
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- umr->mkey_mask = get_umr_reg_mr_mask();
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+ umr->mkey_mask = get_umr_reg_mr_mask(atomic);
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} else {
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umr->mkey_mask = get_umr_unreg_mr_mask();
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}
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@@ -4025,7 +4027,7 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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}
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qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
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ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
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- set_reg_umr_segment(seg, wr);
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+ set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
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seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
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size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
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if (unlikely((seg == qend)))
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