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@@ -17,6 +17,7 @@
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#include <linux/irqreturn.h>
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#include <linux/irqreturn.h>
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#include <linux/usb.h>
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#include <linux/usb.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/gadget.h>
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+#include <linux/usb/otg-fsm.h>
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/******************************************************************************
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/******************************************************************************
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* DEFINE
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* DEFINE
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@@ -139,6 +140,7 @@ struct hw_bank {
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* @roles: array of supported roles for this controller
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* @roles: array of supported roles for this controller
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* @role: current role
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* @role: current role
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* @is_otg: if the device is otg-capable
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* @is_otg: if the device is otg-capable
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+ * @fsm: otg finite state machine
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* @work: work for role changing
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* @work: work for role changing
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* @wq: workqueue thread
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* @wq: workqueue thread
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* @qh_pool: allocation pool for queue heads
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* @qh_pool: allocation pool for queue heads
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@@ -174,6 +176,7 @@ struct ci_hdrc {
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struct ci_role_driver *roles[CI_ROLE_END];
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struct ci_role_driver *roles[CI_ROLE_END];
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enum ci_role role;
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enum ci_role role;
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bool is_otg;
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bool is_otg;
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+ struct otg_fsm fsm;
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struct work_struct work;
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struct work_struct work;
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struct workqueue_struct *wq;
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struct workqueue_struct *wq;
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@@ -319,6 +322,20 @@ static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
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return (val & mask) >> __ffs(mask);
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return (val & mask) >> __ffs(mask);
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}
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}
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+/**
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+ * ci_otg_is_fsm_mode: runtime check if otg controller
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+ * is in otg fsm mode.
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+ */
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+static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
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+{
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+#ifdef CONFIG_USB_OTG_FSM
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+ return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
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+ ci->roles[CI_ROLE_GADGET];
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+#else
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+ return false;
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+#endif
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+}
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+
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u32 hw_read_intr_enable(struct ci_hdrc *ci);
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u32 hw_read_intr_enable(struct ci_hdrc *ci);
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u32 hw_read_intr_status(struct ci_hdrc *ci);
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u32 hw_read_intr_status(struct ci_hdrc *ci);
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