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@@ -4063,6 +4063,13 @@ static int bnx2x_setup_rss(struct bnx2x *bp,
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if (test_bit(BNX2X_RSS_GRE_INNER_HDRS, &p->rss_flags))
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caps |= ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY;
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+ /* RSS keys */
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+ if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) {
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+ memcpy(&data->rss_key[0], &p->rss_key[0],
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+ sizeof(data->rss_key));
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+ caps |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY;
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+ }
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+
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data->capabilities = cpu_to_le16(caps);
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/* Hashing mask */
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@@ -4084,13 +4091,6 @@ static int bnx2x_setup_rss(struct bnx2x *bp,
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if (netif_msg_ifup(bp))
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bnx2x_debug_print_ind_table(bp, p);
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- /* RSS keys */
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- if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) {
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- memcpy(&data->rss_key[0], &p->rss_key[0],
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- sizeof(data->rss_key));
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- data->capabilities |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY;
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- }
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-
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/* No need for an explicit memory barrier here as long as we
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* ensure the ordering of writing to the SPQ element
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* and updating of the SPQ producer which involves a memory
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