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@@ -1,4 +1,5 @@
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/*
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+ * Copyright 2017 NXP
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* Copyright 2011,2016 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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@@ -47,6 +48,7 @@
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#define PROFILE_SEL 0x10
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#define MMDC_MADPCR0 0x410
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+#define MMDC_MADPCR1 0x414
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#define MMDC_MADPSR0 0x418
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#define MMDC_MADPSR1 0x41C
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#define MMDC_MADPSR2 0x420
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@@ -57,6 +59,7 @@
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#define MMDC_NUM_COUNTERS 6
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#define MMDC_FLAG_PROFILE_SEL 0x1
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+#define MMDC_PRF_AXI_ID_CLEAR 0x0
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#define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu)
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@@ -161,8 +164,11 @@ static struct attribute_group mmdc_pmu_events_attr_group = {
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};
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PMU_FORMAT_ATTR(event, "config:0-63");
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+PMU_FORMAT_ATTR(axi_id, "config1:0-63");
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+
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static struct attribute *mmdc_pmu_format_attrs[] = {
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&format_attr_event.attr,
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+ &format_attr_axi_id.attr,
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NULL,
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};
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@@ -345,6 +351,14 @@ static void mmdc_pmu_event_start(struct perf_event *event, int flags)
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writel(DBG_RST, reg);
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+ /*
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+ * Write the AXI id parameter to MADPCR1.
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+ */
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+ val = event->attr.config1;
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+ reg = mmdc_base + MMDC_MADPCR1;
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+ writel(val, reg);
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+
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+ reg = mmdc_base + MMDC_MADPCR0;
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val = DBG_EN;
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if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL)
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val |= PROFILE_SEL;
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@@ -382,6 +396,10 @@ static void mmdc_pmu_event_stop(struct perf_event *event, int flags)
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reg = mmdc_base + MMDC_MADPCR0;
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writel(PRF_FRZ, reg);
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+
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+ reg = mmdc_base + MMDC_MADPCR1;
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+ writel(MMDC_PRF_AXI_ID_CLEAR, reg);
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+
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mmdc_pmu_event_update(event);
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}
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