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@@ -27,6 +27,7 @@
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/* banks shared by multiple phys */
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#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
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#define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
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+#define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
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/* u2 phy bank */
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#define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
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/* u3/pcie/sata phy banks */
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@@ -762,7 +763,7 @@ static void phy_v1_banks_init(struct mtk_tphy *tphy,
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case PHY_TYPE_USB3:
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case PHY_TYPE_PCIE:
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u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
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- u3_banks->chip = NULL;
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+ u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
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u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
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u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
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break;
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