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@@ -165,24 +165,6 @@ int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
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return ret;
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}
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-int mv88e6xxx_config_prio(struct dsa_switch *ds)
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-{
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- /* Configure the IP ToS mapping registers. */
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- REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
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- REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
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- REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
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- REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
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- REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
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- REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
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- REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
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- REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
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-
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- /* Configure the IEEE 802.1p priority mapping register. */
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- REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
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-
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- return 0;
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-}
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-
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int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
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{
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REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
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@@ -434,14 +416,100 @@ void mv88e6xxx_poll_link(struct dsa_switch *ds)
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}
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}
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+static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
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+{
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+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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+
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+ switch (ps->id) {
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+ case PORT_SWITCH_ID_6031:
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+ case PORT_SWITCH_ID_6061:
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+ case PORT_SWITCH_ID_6035:
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+ case PORT_SWITCH_ID_6065:
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+ return true;
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+ }
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+ return false;
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+}
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+
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+static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
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+{
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+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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+
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+ switch (ps->id) {
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+ case PORT_SWITCH_ID_6092:
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+ case PORT_SWITCH_ID_6095:
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+ return true;
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+ }
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+ return false;
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+}
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+
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+static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
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+{
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+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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+
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+ switch (ps->id) {
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+ case PORT_SWITCH_ID_6046:
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+ case PORT_SWITCH_ID_6085:
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+ case PORT_SWITCH_ID_6096:
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+ case PORT_SWITCH_ID_6097:
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+ return true;
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+ }
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+ return false;
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+}
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+
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+static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
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+{
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+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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+
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+ switch (ps->id) {
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+ case PORT_SWITCH_ID_6123:
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+ case PORT_SWITCH_ID_6161:
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+ case PORT_SWITCH_ID_6165:
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+ return true;
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+ }
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+ return false;
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+}
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+
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+static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
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+{
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+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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+
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+ switch (ps->id) {
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+ case PORT_SWITCH_ID_6121:
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+ case PORT_SWITCH_ID_6122:
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+ case PORT_SWITCH_ID_6152:
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+ case PORT_SWITCH_ID_6155:
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+ case PORT_SWITCH_ID_6182:
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+ case PORT_SWITCH_ID_6185:
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+ case PORT_SWITCH_ID_6108:
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+ case PORT_SWITCH_ID_6131:
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+ return true;
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+ }
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+ return false;
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+}
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+
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+static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
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+{
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+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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+
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+ switch (ps->id) {
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+ case PORT_SWITCH_ID_6171:
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+ case PORT_SWITCH_ID_6175:
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+ case PORT_SWITCH_ID_6350:
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+ case PORT_SWITCH_ID_6351:
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+ return true;
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+ }
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+ return false;
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+}
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+
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static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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switch (ps->id) {
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- case PORT_SWITCH_ID_6352:
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case PORT_SWITCH_ID_6172:
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case PORT_SWITCH_ID_6176:
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+ case PORT_SWITCH_ID_6240:
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+ case PORT_SWITCH_ID_6352:
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return true;
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}
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return false;
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@@ -1241,13 +1309,212 @@ static void mv88e6xxx_bridge_work(struct work_struct *work)
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}
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}
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-int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port)
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+int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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int ret, fid;
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+ u16 reg;
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mutex_lock(&ps->smi_mutex);
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+ if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
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+ mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
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+ mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
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+ mv88e6xxx_6065_family(ds)) {
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+ /* MAC Forcing register: don't force link, speed,
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+ * duplex or flow control state to any particular
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+ * values on physical ports, but force the CPU port
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+ * and all DSA ports to their maximum bandwidth and
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+ * full duplex.
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+ */
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+ reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
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+ if (dsa_is_cpu_port(ds, port) ||
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+ ds->dsa_port_mask & (1 << port)) {
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+ reg |= PORT_PCS_CTRL_FORCE_LINK |
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+ PORT_PCS_CTRL_LINK_UP |
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+ PORT_PCS_CTRL_DUPLEX_FULL |
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+ PORT_PCS_CTRL_FORCE_DUPLEX;
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+ if (mv88e6xxx_6065_family(ds))
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+ reg |= PORT_PCS_CTRL_100;
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+ else
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+ reg |= PORT_PCS_CTRL_1000;
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+ } else {
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+ reg |= PORT_PCS_CTRL_UNFORCED;
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+ }
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+
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+ ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
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+ PORT_PCS_CTRL, reg);
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+ if (ret)
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+ goto abort;
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+ }
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+
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+ /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
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+ * disable Header mode, enable IGMP/MLD snooping, disable VLAN
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+ * tunneling, determine priority by looking at 802.1p and IP
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+ * priority fields (IP prio has precedence), and set STP state
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+ * to Forwarding.
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+ *
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+ * If this is the CPU link, use DSA or EDSA tagging depending
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+ * on which tagging mode was configured.
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+ *
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+ * If this is a link to another switch, use DSA tagging mode.
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+ *
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+ * If this is the upstream port for this switch, enable
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+ * forwarding of unknown unicasts and multicasts.
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+ */
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+ reg = 0;
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+ if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
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+ mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
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+ mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
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+ mv88e6xxx_6185_family(ds))
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+ reg = PORT_CONTROL_IGMP_MLD_SNOOP |
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+ PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
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+ PORT_CONTROL_STATE_FORWARDING;
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+ if (dsa_is_cpu_port(ds, port)) {
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+ if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
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+ reg |= PORT_CONTROL_DSA_TAG;
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+ if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
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+ mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) {
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+ if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
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+ reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
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+ else
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+ reg |= PORT_CONTROL_FRAME_MODE_DSA;
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+ }
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+
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+ if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
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+ mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
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+ mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
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+ mv88e6xxx_6185_family(ds)) {
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+ if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
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+ reg |= PORT_CONTROL_EGRESS_ADD_TAG;
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+ }
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+ }
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+ if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
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+ mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
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+ mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds)) {
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+ if (ds->dsa_port_mask & (1 << port))
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+ reg |= PORT_CONTROL_FRAME_MODE_DSA;
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+ if (port == dsa_upstream_port(ds))
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+ reg |= PORT_CONTROL_FORWARD_UNKNOWN |
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+ PORT_CONTROL_FORWARD_UNKNOWN_MC;
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+ }
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+ if (reg) {
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+ ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
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+ PORT_CONTROL, reg);
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+ if (ret)
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+ goto abort;
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+ }
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+
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+ /* Port Control 2: don't force a good FCS, set the maximum
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+ * frame size to 10240 bytes, don't let the switch add or
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+ * strip 802.1q tags, don't discard tagged or untagged frames
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+ * on this port, do a destination address lookup on all
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+ * received packets as usual, disable ARP mirroring and don't
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+ * send a copy of all transmitted/received frames on this port
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+ * to the CPU.
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+ */
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+ reg = 0;
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+ if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
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+ mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
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+ mv88e6xxx_6095_family(ds))
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+ reg = PORT_CONTROL_2_MAP_DA;
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+
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+ if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
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+ mv88e6xxx_6165_family(ds))
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+ reg |= PORT_CONTROL_2_JUMBO_10240;
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+
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+ if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
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+ /* Set the upstream port this port should use */
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+ reg |= dsa_upstream_port(ds);
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+ /* enable forwarding of unknown multicast addresses to
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+ * the upstream port
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+ */
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+ if (port == dsa_upstream_port(ds))
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+ reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
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+ }
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+
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+ if (reg) {
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+ ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
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+ PORT_CONTROL_2, reg);
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+ if (ret)
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+ goto abort;
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+ }
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+
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+ /* Port Association Vector: when learning source addresses
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+ * of packets, add the address to the address database using
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+ * a port bitmap that has only the bit for this port set and
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+ * the other bits clear.
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+ */
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+ ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR,
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+ 1 << port);
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+ if (ret)
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+ goto abort;
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+
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+ /* Egress rate control 2: disable egress rate control. */
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+ ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
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+ 0x0000);
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+ if (ret)
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+ goto abort;
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+
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+ if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
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+ mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) {
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+ /* Do not limit the period of time that this port can
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+ * be paused for by the remote end or the period of
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+ * time that this port can pause the remote end.
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+ */
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+ ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
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+ PORT_PAUSE_CTRL, 0x0000);
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+ if (ret)
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+ goto abort;
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+
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+ /* Port ATU control: disable limiting the number of
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+ * address database entries that this port is allowed
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+ * to use.
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+ */
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+ ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
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+ PORT_ATU_CONTROL, 0x0000);
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+ /* Priority Override: disable DA, SA and VTU priority
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+ * override.
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+ */
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+ ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
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+ PORT_PRI_OVERRIDE, 0x0000);
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+ if (ret)
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+ goto abort;
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+
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+ /* Port Ethertype: use the Ethertype DSA Ethertype
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+ * value.
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+ */
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+ ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
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+ PORT_ETH_TYPE, ETH_P_EDSA);
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+ if (ret)
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+ goto abort;
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+ /* Tag Remap: use an identity 802.1p prio -> switch
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+ * prio mapping.
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+ */
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+ ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
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+ PORT_TAG_REGMAP_0123, 0x3210);
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+ if (ret)
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+ goto abort;
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+
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+ /* Tag Remap 2: use an identity 802.1p prio -> switch
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+ * prio mapping.
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+ */
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+ ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
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+ PORT_TAG_REGMAP_4567, 0x7654);
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+ if (ret)
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+ goto abort;
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+ }
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+
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+ if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
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+ mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
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+ mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) {
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+ /* Rate Control: disable ingress rate limiting. */
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+ ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
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+ PORT_RATE_CONTROL, 0x0001);
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+ if (ret)
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+ goto abort;
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+ }
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+
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/* Port Control 1: disable trunking, disable sending
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* learning messages to this port.
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*/
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@@ -1298,6 +1565,104 @@ int mv88e6xxx_setup_common(struct dsa_switch *ds)
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return 0;
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}
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+int mv88e6xxx_setup_global(struct dsa_switch *ds)
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+{
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+ struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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+ int i;
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+
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+ /* Set the default address aging time to 5 minutes, and
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+ * enable address learn messages to be sent to all message
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+ * ports.
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+ */
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+ REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
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+ 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
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+
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+ /* Configure the IP ToS mapping registers. */
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+ REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
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+ REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
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+ REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
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+ REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
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+ REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
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+ REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
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+ REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
|
|
|
+ REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
|
|
|
+
|
|
|
+ /* Configure the IEEE 802.1p priority mapping register. */
|
|
|
+ REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
|
|
|
+
|
|
|
+ /* Send all frames with destination addresses matching
|
|
|
+ * 01:80:c2:00:00:0x to the CPU port.
|
|
|
+ */
|
|
|
+ REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
|
|
|
+
|
|
|
+ /* Ignore removed tag data on doubly tagged packets, disable
|
|
|
+ * flow control messages, force flow control priority to the
|
|
|
+ * highest, and send all special multicast frames to the CPU
|
|
|
+ * port at the highest priority.
|
|
|
+ */
|
|
|
+ REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
|
|
|
+ 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
|
|
|
+ GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
|
|
|
+
|
|
|
+ /* Program the DSA routing table. */
|
|
|
+ for (i = 0; i < 32; i++) {
|
|
|
+ int nexthop = 0x1f;
|
|
|
+
|
|
|
+ if (ds->pd->rtable &&
|
|
|
+ i != ds->index && i < ds->dst->pd->nr_chips)
|
|
|
+ nexthop = ds->pd->rtable[i] & 0x1f;
|
|
|
+
|
|
|
+ REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
|
|
|
+ GLOBAL2_DEVICE_MAPPING_UPDATE |
|
|
|
+ (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
|
|
|
+ nexthop);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Clear all trunk masks. */
|
|
|
+ for (i = 0; i < 8; i++)
|
|
|
+ REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
|
|
|
+ 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
|
|
|
+ ((1 << ps->num_ports) - 1));
|
|
|
+
|
|
|
+ /* Clear all trunk mappings. */
|
|
|
+ for (i = 0; i < 16; i++)
|
|
|
+ REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
|
|
|
+ GLOBAL2_TRUNK_MAPPING_UPDATE |
|
|
|
+ (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
|
|
|
+
|
|
|
+ if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
|
|
|
+ mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) {
|
|
|
+ /* Send all frames with destination addresses matching
|
|
|
+ * 01:80:c2:00:00:2x to the CPU port.
|
|
|
+ */
|
|
|
+ REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
|
|
|
+
|
|
|
+ /* Initialise cross-chip port VLAN table to reset
|
|
|
+ * defaults.
|
|
|
+ */
|
|
|
+ REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
|
|
|
+
|
|
|
+ /* Clear the priority override table. */
|
|
|
+ for (i = 0; i < 16; i++)
|
|
|
+ REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
|
|
|
+ 0x8000 | (i << 8));
|
|
|
+ }
|
|
|
+
|
|
|
+ if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
|
|
|
+ mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
|
|
|
+ mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) {
|
|
|
+ /* Disable ingress rate limiting by resetting all
|
|
|
+ * ingress rate limit registers to their initial
|
|
|
+ * state.
|
|
|
+ */
|
|
|
+ for (i = 0; i < ps->num_ports; i++)
|
|
|
+ REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
|
|
|
+ 0x9000 | (i << 8));
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
|
|
|
{
|
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
Andrew Lunn