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@@ -14,7 +14,6 @@
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* 2 of the License, or (at your option) any later version.
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*/
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-#include <asm/asm-prototypes.h>
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/mmu_context.h>
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@@ -34,7 +33,7 @@ enum slb_index {
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KSTACK_INDEX = 1, /* Kernel stack map */
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};
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-static long slb_allocate_user(struct mm_struct *mm, unsigned long ea);
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+extern void slb_allocate(unsigned long ea);
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#define slb_esid_mask(ssize) \
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(((ssize) == MMU_SEGSIZE_256M)? ESID_MASK: ESID_MASK_1T)
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@@ -45,17 +44,11 @@ static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
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return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | index;
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}
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-static inline unsigned long __mk_vsid_data(unsigned long vsid, int ssize,
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- unsigned long flags)
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-{
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- return (vsid << slb_vsid_shift(ssize)) | flags |
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- ((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);
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-}
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-
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static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
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unsigned long flags)
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{
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- return __mk_vsid_data(get_kernel_vsid(ea, ssize), ssize, flags);
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+ return (get_kernel_vsid(ea, ssize) << slb_vsid_shift(ssize)) | flags |
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+ ((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);
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}
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static inline void slb_shadow_update(unsigned long ea, int ssize,
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@@ -122,9 +115,6 @@ void slb_restore_bolted_realmode(void)
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{
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__slb_restore_bolted_realmode();
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get_paca()->slb_cache_ptr = 0;
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-
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- get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
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- get_paca()->slb_used_bitmap = get_paca()->slb_kern_bitmap;
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}
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/*
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@@ -132,6 +122,9 @@ void slb_restore_bolted_realmode(void)
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*/
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void slb_flush_all_realmode(void)
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{
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+ /*
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+ * This flushes all SLB entries including 0, so it must be realmode.
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+ */
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asm volatile("slbmte %0,%0; slbia" : : "r" (0));
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}
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@@ -177,9 +170,6 @@ void slb_flush_and_rebolt(void)
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: "memory");
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get_paca()->slb_cache_ptr = 0;
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-
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- get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
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- get_paca()->slb_used_bitmap = get_paca()->slb_kern_bitmap;
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}
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void slb_save_contents(struct slb_entry *slb_ptr)
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@@ -212,7 +202,7 @@ void slb_dump_contents(struct slb_entry *slb_ptr)
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return;
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pr_err("SLB contents of cpu 0x%x\n", smp_processor_id());
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- pr_err("Last SLB entry inserted at slot %u\n", get_paca()->stab_rr);
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+ pr_err("Last SLB entry inserted at slot %lld\n", get_paca()->stab_rr);
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for (i = 0; i < mmu_slb_size; i++) {
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e = slb_ptr->esid;
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@@ -257,119 +247,41 @@ void slb_vmalloc_update(void)
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slb_flush_and_rebolt();
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}
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-static bool preload_hit(struct thread_info *ti, unsigned long esid)
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-{
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- u8 i;
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-
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- for (i = 0; i < ti->slb_preload_nr; i++) {
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- u8 idx;
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-
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- idx = (ti->slb_preload_tail + i) % SLB_PRELOAD_NR;
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- if (esid == ti->slb_preload_esid[idx])
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- return true;
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- }
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- return false;
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-}
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-
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-static bool preload_add(struct thread_info *ti, unsigned long ea)
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-{
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- unsigned long esid;
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- u8 idx;
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-
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- if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
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- /* EAs are stored >> 28 so 256MB segments don't need clearing */
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- if (ea & ESID_MASK_1T)
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- ea &= ESID_MASK_1T;
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- }
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-
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- esid = ea >> SID_SHIFT;
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-
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- if (preload_hit(ti, esid))
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- return false;
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-
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- idx = (ti->slb_preload_tail + ti->slb_preload_nr) % SLB_PRELOAD_NR;
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- ti->slb_preload_esid[idx] = esid;
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- if (ti->slb_preload_nr == SLB_PRELOAD_NR)
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- ti->slb_preload_tail = (ti->slb_preload_tail + 1) % SLB_PRELOAD_NR;
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- else
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- ti->slb_preload_nr++;
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-
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- return true;
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-}
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-
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-static void preload_age(struct thread_info *ti)
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-{
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- if (!ti->slb_preload_nr)
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- return;
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- ti->slb_preload_nr--;
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- ti->slb_preload_tail = (ti->slb_preload_tail + 1) % SLB_PRELOAD_NR;
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-}
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-
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-void slb_setup_new_exec(void)
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+/* Helper function to compare esids. There are four cases to handle.
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+ * 1. The system is not 1T segment size capable. Use the GET_ESID compare.
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+ * 2. The system is 1T capable, both addresses are < 1T, use the GET_ESID compare.
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+ * 3. The system is 1T capable, only one of the two addresses is > 1T. This is not a match.
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+ * 4. The system is 1T capable, both addresses are > 1T, use the GET_ESID_1T macro to compare.
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+ */
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+static inline int esids_match(unsigned long addr1, unsigned long addr2)
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{
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- struct thread_info *ti = current_thread_info();
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- struct mm_struct *mm = current->mm;
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- unsigned long exec = 0x10000000;
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+ int esid_1t_count;
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- /*
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- * We have no good place to clear the slb preload cache on exec,
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- * flush_thread is about the earliest arch hook but that happens
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- * after we switch to the mm and have aleady preloaded the SLBEs.
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- *
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- * For the most part that's probably okay to use entries from the
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- * previous exec, they will age out if unused. It may turn out to
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- * be an advantage to clear the cache before switching to it,
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- * however.
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- */
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-
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- /*
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- * preload some userspace segments into the SLB.
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- * Almost all 32 and 64bit PowerPC executables are linked at
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- * 0x10000000 so it makes sense to preload this segment.
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- */
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- if (!is_kernel_addr(exec)) {
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- if (preload_add(ti, exec))
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- slb_allocate_user(mm, exec);
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- }
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-
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- /* Libraries and mmaps. */
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- if (!is_kernel_addr(mm->mmap_base)) {
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- if (preload_add(ti, mm->mmap_base))
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- slb_allocate_user(mm, mm->mmap_base);
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- }
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-}
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+ /* System is not 1T segment size capable. */
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+ if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
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+ return (GET_ESID(addr1) == GET_ESID(addr2));
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-void preload_new_slb_context(unsigned long start, unsigned long sp)
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-{
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- struct thread_info *ti = current_thread_info();
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- struct mm_struct *mm = current->mm;
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- unsigned long heap = mm->start_brk;
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+ esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) +
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+ ((addr2 >> SID_SHIFT_1T) != 0));
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- /* Userspace entry address. */
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- if (!is_kernel_addr(start)) {
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- if (preload_add(ti, start))
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- slb_allocate_user(mm, start);
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- }
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+ /* both addresses are < 1T */
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+ if (esid_1t_count == 0)
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+ return (GET_ESID(addr1) == GET_ESID(addr2));
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- /* Top of stack, grows down. */
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- if (!is_kernel_addr(sp)) {
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- if (preload_add(ti, sp))
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- slb_allocate_user(mm, sp);
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- }
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+ /* One address < 1T, the other > 1T. Not a match */
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+ if (esid_1t_count == 1)
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+ return 0;
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- /* Bottom of heap, grows up. */
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- if (heap && !is_kernel_addr(heap)) {
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- if (preload_add(ti, heap))
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- slb_allocate_user(mm, heap);
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- }
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+ /* Both addresses are > 1T. */
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+ return (GET_ESID_1T(addr1) == GET_ESID_1T(addr2));
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}
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-
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/* Flush all user entries from the segment table of the current processor. */
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void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
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{
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- struct thread_info *ti = task_thread_info(tsk);
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- u8 i;
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+ unsigned long pc = KSTK_EIP(tsk);
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+ unsigned long stack = KSTK_ESP(tsk);
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+ unsigned long exec_base;
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/*
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* We need interrupts hard-disabled here, not just soft-disabled,
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@@ -392,6 +304,7 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
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if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
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offset <= SLB_CACHE_ENTRIES) {
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unsigned long slbie_data = 0;
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+ int i;
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asm volatile("isync" : : : "memory");
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for (i = 0; i < offset; i++) {
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@@ -422,60 +335,67 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
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"isync"
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:: "r"(ksp_vsid_data),
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"r"(ksp_esid_data));
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-
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- get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
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}
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get_paca()->slb_cache_ptr = 0;
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}
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- get_paca()->slb_used_bitmap = get_paca()->slb_kern_bitmap;
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+
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+ copy_mm_to_paca(mm);
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/*
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- * We gradually age out SLBs after a number of context switches to
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- * reduce reload overhead of unused entries (like we do with FP/VEC
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- * reload). Each time we wrap 256 switches, take an entry out of the
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- * SLB preload cache.
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+ * preload some userspace segments into the SLB.
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+ * Almost all 32 and 64bit PowerPC executables are linked at
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+ * 0x10000000 so it makes sense to preload this segment.
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*/
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- tsk->thread.load_slb++;
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- if (!tsk->thread.load_slb) {
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- unsigned long pc = KSTK_EIP(tsk);
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+ exec_base = 0x10000000;
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- preload_age(ti);
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- preload_add(ti, pc);
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- }
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+ if (is_kernel_addr(pc) || is_kernel_addr(stack) ||
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+ is_kernel_addr(exec_base))
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+ return;
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- for (i = 0; i < ti->slb_preload_nr; i++) {
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- unsigned long ea;
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- u8 idx;
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+ slb_allocate(pc);
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- idx = (ti->slb_preload_tail + i) % SLB_PRELOAD_NR;
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- ea = (unsigned long)ti->slb_preload_esid[idx] << SID_SHIFT;
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+ if (!esids_match(pc, stack))
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+ slb_allocate(stack);
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- slb_allocate_user(mm, ea);
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- }
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+ if (!esids_match(pc, exec_base) &&
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+ !esids_match(stack, exec_base))
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+ slb_allocate(exec_base);
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}
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-void slb_set_size(u16 size)
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+static inline void patch_slb_encoding(unsigned int *insn_addr,
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+ unsigned int immed)
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{
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- mmu_slb_size = size;
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+
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+ /*
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+ * This function patches either an li or a cmpldi instruction with
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+ * a new immediate value. This relies on the fact that both li
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+ * (which is actually addi) and cmpldi both take a 16-bit immediate
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+ * value, and it is situated in the same location in the instruction,
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+ * ie. bits 16-31 (Big endian bit order) or the lower 16 bits.
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+ * The signedness of the immediate operand differs between the two
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+ * instructions however this code is only ever patching a small value,
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+ * much less than 1 << 15, so we can get away with it.
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+ * To patch the value we read the existing instruction, clear the
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+ * immediate value, and or in our new value, then write the instruction
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+ * back.
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+ */
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+ unsigned int insn = (*insn_addr & 0xffff0000) | immed;
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+ patch_instruction(insn_addr, insn);
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}
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-static void cpu_flush_slb(void *parm)
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-{
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- struct mm_struct *mm = parm;
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- unsigned long flags;
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+extern u32 slb_miss_kernel_load_linear[];
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+extern u32 slb_miss_kernel_load_io[];
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+extern u32 slb_compare_rr_to_size[];
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+extern u32 slb_miss_kernel_load_vmemmap[];
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- if (mm != current->active_mm)
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+void slb_set_size(u16 size)
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+{
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+ if (mmu_slb_size == size)
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return;
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- local_irq_save(flags);
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- slb_flush_and_rebolt();
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- local_irq_restore(flags);
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-}
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-
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-void core_flush_all_slbs(struct mm_struct *mm)
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-{
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- on_each_cpu(cpu_flush_slb, mm, 1);
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+ mmu_slb_size = size;
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+ patch_slb_encoding(slb_compare_rr_to_size, mmu_slb_size);
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}
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void slb_initialize(void)
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@@ -497,16 +417,24 @@ void slb_initialize(void)
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#endif
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if (!slb_encoding_inited) {
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slb_encoding_inited = 1;
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+ patch_slb_encoding(slb_miss_kernel_load_linear,
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+ SLB_VSID_KERNEL | linear_llp);
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+ patch_slb_encoding(slb_miss_kernel_load_io,
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+ SLB_VSID_KERNEL | io_llp);
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+ patch_slb_encoding(slb_compare_rr_to_size,
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+ mmu_slb_size);
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+
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pr_devel("SLB: linear LLP = %04lx\n", linear_llp);
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pr_devel("SLB: io LLP = %04lx\n", io_llp);
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+
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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+ patch_slb_encoding(slb_miss_kernel_load_vmemmap,
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+ SLB_VSID_KERNEL | vmemmap_llp);
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pr_devel("SLB: vmemmap LLP = %04lx\n", vmemmap_llp);
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#endif
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}
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get_paca()->stab_rr = SLB_NUM_BOLTED - 1;
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- get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
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- get_paca()->slb_used_bitmap = get_paca()->slb_kern_bitmap;
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lflags = SLB_VSID_KERNEL | linear_llp;
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@@ -530,13 +458,52 @@ void slb_initialize(void)
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asm volatile("isync":::"memory");
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}
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-static void slb_cache_update(unsigned long esid_data)
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+static void insert_slb_entry(unsigned long vsid, unsigned long ea,
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+ int bpsize, int ssize)
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{
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+ unsigned long flags, vsid_data, esid_data;
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+ enum slb_index index;
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int slb_cache_index;
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if (cpu_has_feature(CPU_FTR_ARCH_300))
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return; /* ISAv3.0B and later does not use slb_cache */
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+ /*
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+ * We are irq disabled, hence should be safe to access PACA.
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+ */
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+ VM_WARN_ON(!irqs_disabled());
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+
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+ /*
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+ * We can't take a PMU exception in the following code, so hard
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+ * disable interrupts.
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+ */
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+ hard_irq_disable();
|
|
|
+
|
|
|
+ index = get_paca()->stab_rr;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * simple round-robin replacement of slb starting at SLB_NUM_BOLTED.
|
|
|
+ */
|
|
|
+ if (index < (mmu_slb_size - 1))
|
|
|
+ index++;
|
|
|
+ else
|
|
|
+ index = SLB_NUM_BOLTED;
|
|
|
+
|
|
|
+ get_paca()->stab_rr = index;
|
|
|
+
|
|
|
+ flags = SLB_VSID_USER | mmu_psize_defs[bpsize].sllp;
|
|
|
+ vsid_data = (vsid << slb_vsid_shift(ssize)) | flags |
|
|
|
+ ((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);
|
|
|
+ esid_data = mk_esid_data(ea, ssize, index);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * No need for an isync before or after this slbmte. The exception
|
|
|
+ * we enter with and the rfid we exit with are context synchronizing.
|
|
|
+ * Also we only handle user segments here.
|
|
|
+ */
|
|
|
+ asm volatile("slbmte %0, %1" : : "r" (vsid_data), "r" (esid_data)
|
|
|
+ : "memory");
|
|
|
+
|
|
|
/*
|
|
|
* Now update slb cache entries
|
|
|
*/
|
|
|
@@ -558,196 +525,58 @@ static void slb_cache_update(unsigned long esid_data)
|
|
|
}
|
|
|
}
|
|
|
|
|
|
-static enum slb_index alloc_slb_index(bool kernel)
|
|
|
+static void handle_multi_context_slb_miss(int context_id, unsigned long ea)
|
|
|
{
|
|
|
- enum slb_index index;
|
|
|
-
|
|
|
- /*
|
|
|
- * The allocation bitmaps can become out of synch with the SLB
|
|
|
- * when the _switch code does slbie when bolting a new stack
|
|
|
- * segment and it must not be anywhere else in the SLB. This leaves
|
|
|
- * a kernel allocated entry that is unused in the SLB. With very
|
|
|
- * large systems or small segment sizes, the bitmaps could slowly
|
|
|
- * fill with these entries. They will eventually be cleared out
|
|
|
- * by the round robin allocator in that case, so it's probably not
|
|
|
- * worth accounting for.
|
|
|
- */
|
|
|
+ struct mm_struct *mm = current->mm;
|
|
|
+ unsigned long vsid;
|
|
|
+ int bpsize;
|
|
|
|
|
|
/*
|
|
|
- * SLBs beyond 32 entries are allocated with stab_rr only
|
|
|
- * POWER7/8/9 have 32 SLB entries, this could be expanded if a
|
|
|
- * future CPU has more.
|
|
|
+ * We are always above 1TB, hence use high user segment size.
|
|
|
*/
|
|
|
- if (get_paca()->slb_used_bitmap != U32_MAX) {
|
|
|
- index = ffz(get_paca()->slb_used_bitmap);
|
|
|
- get_paca()->slb_used_bitmap |= 1U << index;
|
|
|
- if (kernel)
|
|
|
- get_paca()->slb_kern_bitmap |= 1U << index;
|
|
|
- } else {
|
|
|
- /* round-robin replacement of slb starting at SLB_NUM_BOLTED. */
|
|
|
- index = get_paca()->stab_rr;
|
|
|
- if (index < (mmu_slb_size - 1))
|
|
|
- index++;
|
|
|
- else
|
|
|
- index = SLB_NUM_BOLTED;
|
|
|
- get_paca()->stab_rr = index;
|
|
|
- if (index < 32) {
|
|
|
- if (kernel)
|
|
|
- get_paca()->slb_kern_bitmap |= 1U << index;
|
|
|
- else
|
|
|
- get_paca()->slb_kern_bitmap &= ~(1U << index);
|
|
|
- }
|
|
|
- }
|
|
|
- BUG_ON(index < SLB_NUM_BOLTED);
|
|
|
-
|
|
|
- return index;
|
|
|
+ vsid = get_vsid(context_id, ea, mmu_highuser_ssize);
|
|
|
+ bpsize = get_slice_psize(mm, ea);
|
|
|
+ insert_slb_entry(vsid, ea, bpsize, mmu_highuser_ssize);
|
|
|
}
|
|
|
|
|
|
-static long slb_insert_entry(unsigned long ea, unsigned long context,
|
|
|
- unsigned long flags, int ssize, bool kernel)
|
|
|
+void slb_miss_large_addr(struct pt_regs *regs)
|
|
|
{
|
|
|
- unsigned long vsid;
|
|
|
- unsigned long vsid_data, esid_data;
|
|
|
- enum slb_index index;
|
|
|
-
|
|
|
- vsid = get_vsid(context, ea, ssize);
|
|
|
- if (!vsid)
|
|
|
- return -EFAULT;
|
|
|
+ enum ctx_state prev_state = exception_enter();
|
|
|
+ unsigned long ea = regs->dar;
|
|
|
+ int context;
|
|
|
|
|
|
- index = alloc_slb_index(kernel);
|
|
|
-
|
|
|
- vsid_data = __mk_vsid_data(vsid, ssize, flags);
|
|
|
- esid_data = mk_esid_data(ea, ssize, index);
|
|
|
+ if (REGION_ID(ea) != USER_REGION_ID)
|
|
|
+ goto slb_bad_addr;
|
|
|
|
|
|
/*
|
|
|
- * No need for an isync before or after this slbmte. The exception
|
|
|
- * we enter with and the rfid we exit with are context synchronizing.
|
|
|
- * Also we only handle user segments here.
|
|
|
+ * Are we beyound what the page table layout supports ?
|
|
|
*/
|
|
|
- asm volatile("slbmte %0, %1" : : "r" (vsid_data), "r" (esid_data));
|
|
|
+ if ((ea & ~REGION_MASK) >= H_PGTABLE_RANGE)
|
|
|
+ goto slb_bad_addr;
|
|
|
|
|
|
- if (!kernel)
|
|
|
- slb_cache_update(esid_data);
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-static long slb_allocate_kernel(unsigned long ea, unsigned long id)
|
|
|
-{
|
|
|
- unsigned long context;
|
|
|
- unsigned long flags;
|
|
|
- int ssize;
|
|
|
-
|
|
|
- if ((ea & ~REGION_MASK) >= (1ULL << MAX_EA_BITS_PER_CONTEXT))
|
|
|
- return -EFAULT;
|
|
|
-
|
|
|
- if (id == KERNEL_REGION_ID) {
|
|
|
- flags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_linear_psize].sllp;
|
|
|
-#ifdef CONFIG_SPARSEMEM_VMEMMAP
|
|
|
- } else if (id == VMEMMAP_REGION_ID) {
|
|
|
- flags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_vmemmap_psize].sllp;
|
|
|
-#endif
|
|
|
- } else if (id == VMALLOC_REGION_ID) {
|
|
|
- if (ea < H_VMALLOC_END)
|
|
|
- flags = get_paca()->vmalloc_sllp;
|
|
|
- else
|
|
|
- flags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_io_psize].sllp;
|
|
|
- } else {
|
|
|
- return -EFAULT;
|
|
|
- }
|
|
|
-
|
|
|
- ssize = MMU_SEGSIZE_1T;
|
|
|
- if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
|
|
|
- ssize = MMU_SEGSIZE_256M;
|
|
|
-
|
|
|
- context = id - KERNEL_REGION_CONTEXT_OFFSET;
|
|
|
-
|
|
|
- return slb_insert_entry(ea, context, flags, ssize, true);
|
|
|
-}
|
|
|
-
|
|
|
-static long slb_allocate_user(struct mm_struct *mm, unsigned long ea)
|
|
|
-{
|
|
|
- unsigned long context;
|
|
|
- unsigned long flags;
|
|
|
- int bpsize;
|
|
|
- int ssize;
|
|
|
+ /* Lower address should have been handled by asm code */
|
|
|
+ if (ea < (1UL << MAX_EA_BITS_PER_CONTEXT))
|
|
|
+ goto slb_bad_addr;
|
|
|
|
|
|
/*
|
|
|
* consider this as bad access if we take a SLB miss
|
|
|
* on an address above addr limit.
|
|
|
*/
|
|
|
- if (ea >= mm->context.slb_addr_limit)
|
|
|
- return -EFAULT;
|
|
|
+ if (ea >= current->mm->context.slb_addr_limit)
|
|
|
+ goto slb_bad_addr;
|
|
|
|
|
|
- context = get_ea_context(&mm->context, ea);
|
|
|
+ context = get_ea_context(¤t->mm->context, ea);
|
|
|
if (!context)
|
|
|
- return -EFAULT;
|
|
|
-
|
|
|
- if (unlikely(ea >= H_PGTABLE_RANGE)) {
|
|
|
- WARN_ON(1);
|
|
|
- return -EFAULT;
|
|
|
- }
|
|
|
-
|
|
|
- ssize = user_segment_size(ea);
|
|
|
-
|
|
|
- bpsize = get_slice_psize(mm, ea);
|
|
|
- flags = SLB_VSID_USER | mmu_psize_defs[bpsize].sllp;
|
|
|
-
|
|
|
- return slb_insert_entry(ea, context, flags, ssize, false);
|
|
|
-}
|
|
|
-
|
|
|
-long do_slb_fault(struct pt_regs *regs, unsigned long ea)
|
|
|
-{
|
|
|
- unsigned long id = REGION_ID(ea);
|
|
|
-
|
|
|
- /* IRQs are not reconciled here, so can't check irqs_disabled */
|
|
|
- VM_WARN_ON(mfmsr() & MSR_EE);
|
|
|
-
|
|
|
- if (unlikely(!(regs->msr & MSR_RI)))
|
|
|
- return -EINVAL;
|
|
|
-
|
|
|
- /*
|
|
|
- * SLB kernel faults must be very careful not to touch anything
|
|
|
- * that is not bolted. E.g., PACA and global variables are okay,
|
|
|
- * mm->context stuff is not.
|
|
|
- *
|
|
|
- * SLB user faults can access all of kernel memory, but must be
|
|
|
- * careful not to touch things like IRQ state because it is not
|
|
|
- * "reconciled" here. The difficulty is that we must use
|
|
|
- * fast_exception_return to return from kernel SLB faults without
|
|
|
- * looking at possible non-bolted memory. We could test user vs
|
|
|
- * kernel faults in the interrupt handler asm and do a full fault,
|
|
|
- * reconcile, ret_from_except for user faults which would make them
|
|
|
- * first class kernel code. But for performance it's probably nicer
|
|
|
- * if they go via fast_exception_return too.
|
|
|
- */
|
|
|
- if (id >= KERNEL_REGION_ID) {
|
|
|
- return slb_allocate_kernel(ea, id);
|
|
|
- } else {
|
|
|
- struct mm_struct *mm = current->mm;
|
|
|
- long err;
|
|
|
-
|
|
|
- if (unlikely(!mm))
|
|
|
- return -EFAULT;
|
|
|
+ goto slb_bad_addr;
|
|
|
|
|
|
- err = slb_allocate_user(mm, ea);
|
|
|
- if (!err)
|
|
|
- preload_add(current_thread_info(), ea);
|
|
|
-
|
|
|
- return err;
|
|
|
- }
|
|
|
-}
|
|
|
+ handle_multi_context_slb_miss(context, ea);
|
|
|
+ exception_exit(prev_state);
|
|
|
+ return;
|
|
|
|
|
|
-void do_bad_slb_fault(struct pt_regs *regs, unsigned long ea, long err)
|
|
|
-{
|
|
|
- if (err == -EFAULT) {
|
|
|
- if (user_mode(regs))
|
|
|
- _exception(SIGSEGV, regs, SEGV_BNDERR, ea);
|
|
|
- else
|
|
|
- bad_page_fault(regs, ea, SIGSEGV);
|
|
|
- } else if (err == -EINVAL) {
|
|
|
- unrecoverable_exception(regs);
|
|
|
- } else {
|
|
|
- BUG();
|
|
|
- }
|
|
|
+slb_bad_addr:
|
|
|
+ if (user_mode(regs))
|
|
|
+ _exception(SIGSEGV, regs, SEGV_BNDERR, ea);
|
|
|
+ else
|
|
|
+ bad_page_fault(regs, ea, SIGSEGV);
|
|
|
+ exception_exit(prev_state);
|
|
|
}
|
Michael Ellerman