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@@ -355,10 +355,6 @@ static int imx6_pcie_wait_for_link(struct pcie_port *pp)
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usleep_range(100, 1000);
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}
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- dev_err(pp->dev, "phy link never came up\n");
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- dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
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- readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
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- readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
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return -EINVAL;
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}
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@@ -407,8 +403,10 @@ static int imx6_pcie_establish_link(struct pcie_port *pp)
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IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
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ret = imx6_pcie_wait_for_link(pp);
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- if (ret)
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- return ret;
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+ if (ret) {
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+ dev_info(pp->dev, "Link never came up\n");
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+ goto err_reset_phy;
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+ }
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/* Allow Gen2 mode after the link is up. */
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tmp = readl(pp->dbi_base + PCIE_RC_LCR);
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@@ -427,19 +425,28 @@ static int imx6_pcie_establish_link(struct pcie_port *pp)
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ret = imx6_pcie_wait_for_speed_change(pp);
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if (ret) {
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dev_err(pp->dev, "Failed to bring link up!\n");
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- return ret;
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+ goto err_reset_phy;
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}
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/* Make sure link training is finished as well! */
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ret = imx6_pcie_wait_for_link(pp);
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if (ret) {
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dev_err(pp->dev, "Failed to bring link up!\n");
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- return ret;
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+ goto err_reset_phy;
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}
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tmp = readl(pp->dbi_base + PCIE_RC_LCSR);
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dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
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+
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return 0;
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+
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+err_reset_phy:
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+ dev_dbg(pp->dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
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+ readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
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+ readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
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+ imx6_pcie_reset_phy(pp);
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+
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+ return ret;
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}
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static void imx6_pcie_host_init(struct pcie_port *pp)
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@@ -510,11 +517,6 @@ static int imx6_pcie_link_up(struct pcie_port *pp)
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if ((debug_r0 & 0x3f) != 0x0d)
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return 0;
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- dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
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- dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc);
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-
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- imx6_pcie_reset_phy(pp);
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-
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return 0;
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}
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