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@@ -1514,6 +1514,20 @@ static void dsi_pll_calc_dsi_fck(struct dsi_clock_info *cinfo)
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cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
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}
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+static int dsi_wait_hsdiv_ack(struct platform_device *dsidev, u32 hsdiv_ack_mask)
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+{
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+ int t = 100;
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+
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+ while (t-- > 0) {
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+ u32 v = dsi_read_reg(dsidev, DSI_PLL_STATUS);
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+ v &= hsdiv_ack_mask;
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+ if (v == hsdiv_ack_mask)
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+ return 0;
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+ }
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+
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+ return -ETIMEDOUT;
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+}
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+
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int dsi_pll_set_clock_div(struct platform_device *dsidev,
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struct dsi_clock_info *cinfo)
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{
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@@ -1646,6 +1660,13 @@ int dsi_pll_set_clock_div(struct platform_device *dsidev,
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l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
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dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
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+ r = dsi_wait_hsdiv_ack(dsidev, BIT(7) | BIT(8));
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+ if (r) {
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+ DSSERR("failed to enable HSDIV clocks: %d\n", r);
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+ goto err;
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+ }
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+
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+
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DSSDBG("PLL config done\n");
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err:
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return r;
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