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@@ -45,11 +45,6 @@
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#define FW_FNAME_T5 "cxgb4/t5fw.bin"
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#define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
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-#define T5FW_VERSION_MAJOR 0x01
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-#define T5FW_VERSION_MINOR 0x0B
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-#define T5FW_VERSION_MICRO 0x1B
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-#define T5FW_VERSION_BUILD 0x00
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-
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#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
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#define CHELSIO_CHIP_FPGA 0x100
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#define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf)
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@@ -74,6 +69,7 @@ static inline int csio_is_t5(uint16_t chip)
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{ PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
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#include "t4fw_api.h"
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+#include "t4fw_version.h"
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#define FW_VERSION(chip) ( \
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FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
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