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@@ -6677,22 +6677,20 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
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static void compute_m_n(unsigned int m, unsigned int n,
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uint32_t *ret_m, uint32_t *ret_n,
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- bool reduce_m_n)
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+ bool constant_n)
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{
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/*
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- * Reduce M/N as much as possible without loss in precision. Several DP
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- * dongles in particular seem to be fussy about too large *link* M/N
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- * values. The passed in values are more likely to have the least
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- * significant bits zero than M after rounding below, so do this first.
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+ * Several DP dongles in particular seem to be fussy about
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+ * too large link M/N values. Give N value as 0x8000 that
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+ * should be acceptable by specific devices. 0x8000 is the
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+ * specified fixed N value for asynchronous clock mode,
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+ * which the devices expect also in synchronous clock mode.
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*/
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- if (reduce_m_n) {
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- while ((m & 1) == 0 && (n & 1) == 0) {
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- m >>= 1;
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- n >>= 1;
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- }
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- }
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+ if (constant_n)
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+ *ret_n = 0x8000;
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+ else
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+ *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
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- *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
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*ret_m = div_u64((uint64_t) m * *ret_n, n);
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intel_reduce_m_n_ratio(ret_m, ret_n);
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}
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@@ -6701,18 +6699,18 @@ void
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intel_link_compute_m_n(int bits_per_pixel, int nlanes,
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int pixel_clock, int link_clock,
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struct intel_link_m_n *m_n,
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- bool reduce_m_n)
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+ bool constant_n)
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{
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m_n->tu = 64;
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compute_m_n(bits_per_pixel * pixel_clock,
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link_clock * nlanes * 8,
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&m_n->gmch_m, &m_n->gmch_n,
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- reduce_m_n);
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+ constant_n);
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compute_m_n(pixel_clock, link_clock,
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&m_n->link_m, &m_n->link_n,
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- reduce_m_n);
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+ constant_n);
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}
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static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
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