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@@ -35,7 +35,7 @@
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#define MSR_IA32_PERFCTR0 0x000000c1
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#define MSR_IA32_PERFCTR0 0x000000c1
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#define MSR_IA32_PERFCTR1 0x000000c2
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#define MSR_IA32_PERFCTR1 0x000000c2
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#define MSR_FSB_FREQ 0x000000cd
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#define MSR_FSB_FREQ 0x000000cd
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-#define MSR_NHM_PLATFORM_INFO 0x000000ce
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+#define MSR_PLATFORM_INFO 0x000000ce
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#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
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#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
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#define NHM_C3_AUTO_DEMOTE (1UL << 25)
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#define NHM_C3_AUTO_DEMOTE (1UL << 25)
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@@ -44,7 +44,6 @@
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#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
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#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
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#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
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#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
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-#define MSR_PLATFORM_INFO 0x000000ce
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#define MSR_MTRRcap 0x000000fe
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#define MSR_MTRRcap 0x000000fe
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#define MSR_IA32_BBL_CR_CTL 0x00000119
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#define MSR_IA32_BBL_CR_CTL 0x00000119
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#define MSR_IA32_BBL_CR_CTL3 0x0000011e
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#define MSR_IA32_BBL_CR_CTL3 0x0000011e
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