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@@ -17,6 +17,8 @@
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* (ICP) P16R16-DIO [p16r16dio]
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* (Advantech) PCL-733 [pcl733]
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* (Advantech) PCL-734 [pcl734]
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+ * (Diamond Systems) OPMM-1616-XT [opmm-1616-xt]
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+ * (Diamond Systems) PEARL-MM-P [prearl-mm-p]
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* Author: José Luis Sánchez (jsanchezv@teleline.es)
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* Status: untested
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*
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@@ -70,6 +72,27 @@
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* BASE+1 Isolated outputs 8-15 (write) or inputs 8-15 (read)
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* BASE+2 Isolated outputs 16-23 (write) or inputs 16-23 (read)
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* BASE+3 Isolated outputs 24-31 (write) or inputs 24-31 (read)
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+ *
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+ * The opmm-1616-xt board has this register mapping:
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+ *
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+ * BASE+0 Isolated outputs 0-7 (write) (read back)
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+ * BASE+1 Isolated outputs 8-15 (write) (read back)
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+ * BASE+2 Isolated inputs 0-7 (read)
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+ * BASE+3 Isolated inputs 8-15 (read)
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+ *
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+ * These registers are not currently supported:
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+ *
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+ * BASE+2 Relay select register (write)
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+ * BASE+3 Board reset control register (write)
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+ * BASE+4 Interrupt control register (write)
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+ * BASE+4 Change detect 7-0 status register (read)
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+ * BASE+5 LED control register (write)
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+ * BASE+5 Change detect 15-8 status register (read)
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+ *
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+ * The pearl-mm-p board has this register mapping:
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+ *
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+ * BASE+0 Isolated outputs 0-7 (write)
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+ * BASE+1 Isolated outputs 8-15 (write)
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*/
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struct pcl730_board {
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@@ -158,6 +181,19 @@ static const struct pcl730_board pcl730_boards[] = {
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.io_range = 0x04,
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.n_subdevs = 1,
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.n_iso_out_chan = 32,
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+ }, {
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+ .name = "opmm-1616-xt",
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+ .io_range = 0x10,
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+ .is_acl7225b = 1,
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+ .has_readback = 1,
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+ .n_subdevs = 2,
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+ .n_iso_out_chan = 16,
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+ .n_iso_in_chan = 16,
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+ }, {
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+ .name = "pearl-mm-p",
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+ .io_range = 0x02,
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+ .n_subdevs = 1,
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+ .n_iso_out_chan = 16,
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},
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};
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