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@@ -1102,6 +1102,7 @@ struct dwc2_hsotg {
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/* DWC OTG HW Release versions */
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/* DWC OTG HW Release versions */
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#define DWC2_CORE_REV_2_71a 0x4f54271a
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#define DWC2_CORE_REV_2_71a 0x4f54271a
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+#define DWC2_CORE_REV_2_72a 0x4f54272a
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#define DWC2_CORE_REV_2_80a 0x4f54280a
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#define DWC2_CORE_REV_2_80a 0x4f54280a
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#define DWC2_CORE_REV_2_90a 0x4f54290a
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#define DWC2_CORE_REV_2_90a 0x4f54290a
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#define DWC2_CORE_REV_2_91a 0x4f54291a
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#define DWC2_CORE_REV_2_91a 0x4f54291a
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@@ -1109,6 +1110,7 @@ struct dwc2_hsotg {
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#define DWC2_CORE_REV_2_94a 0x4f54294a
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#define DWC2_CORE_REV_2_94a 0x4f54294a
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#define DWC2_CORE_REV_3_00a 0x4f54300a
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#define DWC2_CORE_REV_3_00a 0x4f54300a
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#define DWC2_CORE_REV_3_10a 0x4f54310a
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#define DWC2_CORE_REV_3_10a 0x4f54310a
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+#define DWC2_CORE_REV_4_00a 0x4f54400a
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#define DWC2_FS_IOT_REV_1_00a 0x5531100a
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#define DWC2_FS_IOT_REV_1_00a 0x5531100a
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#define DWC2_HS_IOT_REV_1_00a 0x5532100a
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#define DWC2_HS_IOT_REV_1_00a 0x5532100a
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