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drm/amd/powerplay: fix pcie max lane define error

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu 8 years ago
parent
e71b7ae673
commit
510c2558b9
1 changed files with 1 additions and 1 deletions
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  1. 1 1
      drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h

+ 1 - 1
drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
View File 

@@ -297,7 +297,7 @@ typedef enum PP_PCIEGen PP_PCIEGen;
 
 #define PP_Min_PCIEGen     PP_PCIEGen1
 
 #define PP_Min_PCIEGen     PP_PCIEGen1
 
 #define PP_Max_PCIEGen     PP_PCIEGen3
 
 #define PP_Max_PCIEGen     PP_PCIEGen3
 
 #define PP_Min_PCIELane    1
 
 #define PP_Min_PCIELane    1
 
-#define PP_Max_PCIELane    32
 
+#define PP_Max_PCIELane    16
 
 
 
 enum phm_clock_Type {
 
 enum phm_clock_Type {
 
 	PHM_DispClock = 1,
 
 	PHM_DispClock = 1,