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@@ -66,6 +66,7 @@ enum dma_transaction_type {
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DMA_XOR_VAL,
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DMA_PQ_VAL,
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DMA_MEMSET,
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+ DMA_MEMSET_SG,
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DMA_INTERRUPT,
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DMA_SG,
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DMA_PRIVATE,
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@@ -630,6 +631,7 @@ enum dmaengine_alignment {
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* @device_prep_dma_pq: prepares a pq operation
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* @device_prep_dma_pq_val: prepares a pqzero_sum operation
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* @device_prep_dma_memset: prepares a memset operation
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+ * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
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* @device_prep_dma_interrupt: prepares an end of chain interrupt operation
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* @device_prep_slave_sg: prepares a slave dma operation
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* @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
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@@ -696,6 +698,9 @@ struct dma_device {
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struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
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struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
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unsigned long flags);
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+ struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
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+ struct dma_chan *chan, struct scatterlist *sg,
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+ unsigned int nents, int value, unsigned long flags);
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struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
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struct dma_chan *chan, unsigned long flags);
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struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
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