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+/*
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+ * Copyright 2014 Roy Spliet
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in
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+ * all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ *
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+ * Authors: Roy Spliet <rspliet@eclipso.eu>
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+ * Ben Skeggs
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+ */
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+
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+#include <subdev/bios.h>
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+#include "priv.h"
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+
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+struct ramxlat {
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+ int id;
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+ u8 enc;
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+};
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+
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+static inline int
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+ramxlat(const struct ramxlat *xlat, int id)
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+{
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+ while (xlat->id >= 0) {
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+ if (xlat->id == id)
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+ return xlat->enc;
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+ xlat++;
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+ }
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+ return -EINVAL;
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+}
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+
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+static const struct ramxlat
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+ramddr2_cl[] = {
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+ { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 },
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+ /* The following are available in some, but not all DDR2 docs */
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+ { 7, 7 },
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+ { -1 }
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+};
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+
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+static const struct ramxlat
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+ramddr2_wr[] = {
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+ { 2, 1 }, { 3, 2 }, { 4, 3 }, { 5, 4 }, { 6, 5 },
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+ /* The following are available in some, but not all DDR2 docs */
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+ { 7, 6 },
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+ { -1 }
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+};
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+
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+int
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+nouveau_sddr2_calc(struct nouveau_ram *ram)
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+{
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+ struct nouveau_bios *bios = nouveau_bios(ram);
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+ int CL, WR, DLL = 0, ODT = 0;
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+
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+ switch (!!ram->timing.data * ram->timing.version) {
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+ case 0x10:
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+ CL = nv_ro08(bios, ram->timing.data + 0x02);
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+ WR = nv_ro08(bios, ram->timing.data + 0x00);
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+ DLL = !(nv_ro08(bios, ram->ramcfg.data + 0x02) & 0x40);
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+ ODT = nv_ro08(bios, ram->timing.data + 0x0e) & 0x03;
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+ break;
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+ case 0x20:
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+ CL = nv_ro08(bios, ram->timing.data + 0x04) & 0x1f;
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+ WR = nv_ro08(bios, ram->timing.data + 0x0a) & 0x7f;
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+ break;
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+ default:
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+ return -ENOSYS;
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+ }
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+
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+ CL = ramxlat(ramddr2_cl, CL);
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+ WR = ramxlat(ramddr2_wr, WR);
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+ if (CL < 0 || WR < 0)
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+ return -EINVAL;
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+
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+ ram->mr[0] &= ~0xf70;
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+ ram->mr[0] |= (WR & 0x07) << 9;
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+ ram->mr[0] |= (CL & 0x07) << 4;
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+
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+ ram->mr[1] &= ~0x045;
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+ ram->mr[1] |= (ODT & 0x1) << 2;
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+ ram->mr[1] |= (ODT & 0x2) << 5;
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+ ram->mr[1] |= !DLL;
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+ return 0;
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+}
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