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@@ -314,15 +314,22 @@ void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
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void b43_phy_put_into_reset(struct b43_wldev *dev)
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{
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-#ifdef CONFIG_B43_SSB
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u32 tmp;
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-#endif
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switch (dev->dev->bus_type) {
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#ifdef CONFIG_B43_BCMA
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case B43_BUS_BCMA:
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- b43err(dev->wl,
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- "Putting PHY into reset not supported on BCMA\n");
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+ tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
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+ tmp &= ~B43_BCMA_IOCTL_GMODE;
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+ tmp |= B43_BCMA_IOCTL_PHY_RESET;
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+ tmp |= BCMA_IOCTL_FGC;
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+ bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
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+ udelay(1);
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+
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+ tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
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+ tmp &= ~BCMA_IOCTL_FGC;
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+ bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
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+ udelay(1);
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break;
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#endif
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#ifdef CONFIG_B43_SSB
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@@ -332,14 +339,58 @@ void b43_phy_put_into_reset(struct b43_wldev *dev)
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tmp |= B43_TMSLOW_PHYRESET;
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tmp |= SSB_TMSLOW_FGC;
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ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
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- msleep(1);
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+ usleep_range(1000, 2000);
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tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
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tmp &= ~SSB_TMSLOW_FGC;
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- tmp |= B43_TMSLOW_PHYRESET;
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ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
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- msleep(1);
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+ usleep_range(1000, 2000);
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+
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+ break;
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+#endif
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+ }
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+}
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+void b43_phy_take_out_of_reset(struct b43_wldev *dev)
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+{
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+ u32 tmp;
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+
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+ switch (dev->dev->bus_type) {
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+#ifdef CONFIG_B43_BCMA
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+ case B43_BUS_BCMA:
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+ /* Unset reset bit (with forcing clock) */
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+ tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
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+ tmp &= ~B43_BCMA_IOCTL_PHY_RESET;
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+ tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
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+ tmp |= BCMA_IOCTL_FGC;
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+ bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
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+ udelay(1);
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+
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+ /* Do not force clock anymore */
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+ tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
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+ tmp &= ~BCMA_IOCTL_FGC;
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+ tmp |= B43_BCMA_IOCTL_PHY_CLKEN;
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+ bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
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+ udelay(1);
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+ break;
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+#endif
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+#ifdef CONFIG_B43_SSB
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+ case B43_BUS_SSB:
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+ /* Unset reset bit (with forcing clock) */
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+ tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
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+ tmp &= ~B43_TMSLOW_PHYRESET;
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+ tmp &= ~B43_TMSLOW_PHYCLKEN;
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+ tmp |= SSB_TMSLOW_FGC;
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+ ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
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+ ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
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+ usleep_range(1000, 2000);
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+
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+ tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
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+ tmp &= ~SSB_TMSLOW_FGC;
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+ tmp |= B43_TMSLOW_PHYCLKEN;
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+ ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
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+ ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
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+ usleep_range(1000, 2000);
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break;
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#endif
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}
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