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@@ -169,7 +169,7 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
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static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
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u32 cpol, u32 cpha,
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- u32 tx_hi_z, u32 lsb_first)
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+ u32 tx_hi_z, u32 lsb_first, u32 cs_high)
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{
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u32 tmp;
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int edge;
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@@ -182,8 +182,12 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
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* 1 1 11 11 1 1
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*/
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sh_msiof_write(p, FCTR, 0);
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- sh_msiof_write(p, TMDR1, 0xe2000005 | (lsb_first << 24));
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- sh_msiof_write(p, RMDR1, 0x22000005 | (lsb_first << 24));
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+
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+ tmp = 0;
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+ tmp |= !cs_high << 25;
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+ tmp |= lsb_first << 24;
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+ sh_msiof_write(p, TMDR1, 0xe0000005 | tmp);
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+ sh_msiof_write(p, RMDR1, 0x20000005 | tmp);
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tmp = 0xa0000000;
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tmp |= cpol << 30; /* TSCKIZ */
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@@ -417,7 +421,8 @@ static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on)
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sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
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!!(spi->mode & SPI_CPHA),
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!!(spi->mode & SPI_3WIRE),
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- !!(spi->mode & SPI_LSB_FIRST));
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+ !!(spi->mode & SPI_LSB_FIRST),
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+ !!(spi->mode & SPI_CS_HIGH));
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}
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/* use spi->controller data for CS (same strategy as spi_gpio) */
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