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@@ -34,9 +34,7 @@
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#include "dce/dce_hwseq.h"
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#include "gpio_service_interface.h"
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-#if defined(CONFIG_DRM_AMD_DC_FBC)
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#include "dce110_compressor.h"
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-#endif
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#include "bios/bios_parser_helper.h"
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#include "timing_generator.h"
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@@ -1497,10 +1495,8 @@ static void power_down_all_hw_blocks(struct dc *dc)
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power_down_clock_sources(dc);
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-#if defined(CONFIG_DRM_AMD_DC_FBC)
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if (dc->fbc_compressor)
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dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
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-#endif
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}
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static void disable_vga_and_power_gate_all_controllers(
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@@ -1742,9 +1738,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
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if (events->force_trigger)
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value |= 0x1;
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-#if defined(CONFIG_DRM_AMD_DC_FBC)
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value |= 0x84;
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-#endif
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for (i = 0; i < num_pipes; i++)
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pipe_ctx[i]->stream_res.tg->funcs->
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@@ -1872,8 +1866,6 @@ static void apply_min_clocks(
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}
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}
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-#if defined(CONFIG_DRM_AMD_DC_FBC)
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-
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/*
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* Check if FBC can be enabled
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*/
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@@ -1952,7 +1944,6 @@ static void enable_fbc(struct dc *dc,
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compr->funcs->enable_fbc(compr, ¶ms);
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}
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}
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-#endif
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static void dce110_reset_hw_ctx_wrap(
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struct dc *dc,
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@@ -2129,10 +2120,9 @@ enum dc_status dce110_apply_ctx_to_hw(
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set_safe_displaymarks(&context->res_ctx, dc->res_pool);
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-#if defined(CONFIG_DRM_AMD_DC_FBC)
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if (dc->fbc_compressor)
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dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
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-#endif
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+
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/*TODO: when pplib works*/
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apply_min_clocks(dc, context, &clocks_state, true);
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@@ -2210,12 +2200,9 @@ enum dc_status dce110_apply_ctx_to_hw(
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dcb->funcs->set_scratch_critical_state(dcb, false);
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-#if defined(CONFIG_DRM_AMD_DC_FBC)
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if (dc->fbc_compressor)
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enable_fbc(dc, context);
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-#endif
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-
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return DC_OK;
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}
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@@ -2530,10 +2517,9 @@ static void init_hw(struct dc *dc)
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abm->funcs->init_backlight(abm);
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abm->funcs->abm_init(abm);
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}
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-#if defined(CONFIG_DRM_AMD_DC_FBC)
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+
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if (dc->fbc_compressor)
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dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
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-#endif
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}
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@@ -2719,9 +2705,7 @@ static void dce110_program_front_end_for_pipe(
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struct dc_plane_state *plane_state = pipe_ctx->plane_state;
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struct xfm_grph_csc_adjustment adjust;
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struct out_csc_color_matrix tbl_entry;
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-#if defined(CONFIG_DRM_AMD_DC_FBC)
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unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
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-#endif
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unsigned int i;
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DC_LOGGER_INIT();
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memset(&tbl_entry, 0, sizeof(tbl_entry));
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@@ -2762,7 +2746,6 @@ static void dce110_program_front_end_for_pipe(
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program_scaler(dc, pipe_ctx);
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-#if defined(CONFIG_DRM_AMD_DC_FBC)
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/* fbc not applicable on Underlay pipe */
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if (dc->fbc_compressor && old_pipe->stream &&
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pipe_ctx->pipe_idx != underlay_idx) {
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@@ -2771,7 +2754,6 @@ static void dce110_program_front_end_for_pipe(
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else
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enable_fbc(dc, dc->current_state);
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}
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-#endif
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mi->funcs->mem_input_program_surface_config(
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mi,
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