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@@ -138,6 +138,24 @@ struct amdgpu_prt_cb {
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struct dma_fence_cb cb;
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};
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+/**
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+ * amdgpu_vm_level_shift - return the addr shift for each level
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+ *
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+ * @adev: amdgpu_device pointer
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+ *
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+ * Returns the number of bits the pfn needs to be right shifted for a level.
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+ */
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+static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
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+ unsigned level)
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+{
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+ if (level != adev->vm_manager.num_level)
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+ return 9 * (adev->vm_manager.num_level - level - 1) +
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+ adev->vm_manager.block_size;
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+ else
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+ /* For the page tables on the leaves */
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+ return 0;
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+}
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+
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/**
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* amdgpu_vm_num_entries - return the number of entries in a PD/PT
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*
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@@ -288,8 +306,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
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uint64_t saddr, uint64_t eaddr,
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unsigned level)
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{
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- unsigned shift = (adev->vm_manager.num_level - level) *
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- adev->vm_manager.block_size;
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+ unsigned shift = amdgpu_vm_level_shift(adev, level);
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unsigned pt_idx, from, to;
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int r;
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u64 flags;
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@@ -1302,18 +1319,19 @@ void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr,
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struct amdgpu_vm_pt **entry,
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struct amdgpu_vm_pt **parent)
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{
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- unsigned idx, level = p->adev->vm_manager.num_level;
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+ unsigned level = 0;
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*parent = NULL;
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*entry = &p->vm->root;
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while ((*entry)->entries) {
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- idx = addr >> (p->adev->vm_manager.block_size * level--);
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+ unsigned idx = addr >> amdgpu_vm_level_shift(p->adev, level++);
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+
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idx %= amdgpu_bo_size((*entry)->base.bo) / 8;
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*parent = *entry;
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*entry = &(*entry)->entries[idx];
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}
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- if (level)
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+ if (level != p->adev->vm_manager.num_level)
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*entry = NULL;
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}
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