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@@ -0,0 +1,1018 @@
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+/******************************************************************************
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+ *
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+ * This file is provided under a dual BSD/GPLv2 license. When using or
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+ * redistributing this file, you may do so under either license.
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+ *
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+ * GPL LICENSE SUMMARY
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+ *
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+ * Copyright(c) 2017 Intel Deutschland GmbH
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of version 2 of the GNU General Public License as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful, but
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+ * WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ * General Public License for more details.
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+ *
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+ * BSD LICENSE
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+ *
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+ * Copyright(c) 2017 Intel Deutschland GmbH
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+ * All rights reserved.
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions
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+ * are met:
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+ *
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+ * * Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ * * Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in
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+ * the documentation and/or other materials provided with the
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+ * distribution.
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+ * * Neither the name Intel Corporation nor the names of its
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+ * contributors may be used to endorse or promote products derived
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+ * from this software without specific prior written permission.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ *
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+ *****************************************************************************/
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+#include <linux/pm_runtime.h>
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+
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+#include "iwl-debug.h"
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+#include "iwl-csr.h"
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+#include "iwl-io.h"
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+#include "internal.h"
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+#include "mvm/fw-api.h"
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+
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+ /*
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+ * iwl_pcie_gen2_tx_stop - Stop all Tx DMA channels
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+ */
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+void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans)
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+{
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+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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+ int txq_id;
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+
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+ /*
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+ * This function can be called before the op_mode disabled the
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+ * queues. This happens when we have an rfkill interrupt.
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+ * Since we stop Tx altogether - mark the queues as stopped.
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+ */
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+ memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
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+ memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
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+
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+ /* Unmap DMA from host system and free skb's */
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+ for (txq_id = 0; txq_id < ARRAY_SIZE(trans_pcie->txq); txq_id++) {
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+ if (!trans_pcie->txq[txq_id])
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+ continue;
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+ iwl_pcie_gen2_txq_unmap(trans, txq_id);
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+ }
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+}
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+
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+/*
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+ * iwl_pcie_txq_update_byte_tbl - Set up entry in Tx byte-count array
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+ */
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+static void iwl_pcie_gen2_update_byte_tbl(struct iwl_txq *txq, u16 byte_cnt,
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+ int num_tbs)
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+{
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+ struct iwlagn_scd_bc_tbl *scd_bc_tbl = txq->bc_tbl.addr;
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+ int write_ptr = txq->write_ptr;
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+ u8 filled_tfd_size, num_fetch_chunks;
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+ u16 len = byte_cnt;
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+ __le16 bc_ent;
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+
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+ len = DIV_ROUND_UP(len, 4);
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+
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+ if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
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+ return;
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+
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+ filled_tfd_size = offsetof(struct iwl_tfh_tfd, tbs) +
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+ num_tbs * sizeof(struct iwl_tfh_tb);
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+ /*
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+ * filled_tfd_size contains the number of filled bytes in the TFD.
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+ * Dividing it by 64 will give the number of chunks to fetch
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+ * to SRAM- 0 for one chunk, 1 for 2 and so on.
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+ * If, for example, TFD contains only 3 TBs then 32 bytes
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+ * of the TFD are used, and only one chunk of 64 bytes should
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+ * be fetched
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+ */
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+ num_fetch_chunks = DIV_ROUND_UP(filled_tfd_size, 64) - 1;
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+
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+ bc_ent = cpu_to_le16(len | (num_fetch_chunks << 12));
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+ scd_bc_tbl->tfd_offset[write_ptr] = bc_ent;
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+}
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+
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+/*
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+ * iwl_pcie_gen2_txq_inc_wr_ptr - Send new write index to hardware
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+ */
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+static void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans,
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+ struct iwl_txq *txq)
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+{
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+ lockdep_assert_held(&txq->lock);
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+
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+ IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq->id, txq->write_ptr);
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+
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+ /*
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+ * if not in power-save mode, uCode will never sleep when we're
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+ * trying to tx (during RFKILL, we're not trying to tx).
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+ */
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+ iwl_write32(trans, HBUS_TARG_WRPTR, txq->write_ptr | (txq->id << 16));
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+}
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+
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+static u8 iwl_pcie_gen2_get_num_tbs(struct iwl_trans *trans,
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+ struct iwl_tfh_tfd *tfd)
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+{
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+ return le16_to_cpu(tfd->num_tbs) & 0x1f;
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+}
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+
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+static void iwl_pcie_gen2_tfd_unmap(struct iwl_trans *trans,
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+ struct iwl_cmd_meta *meta,
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+ struct iwl_tfh_tfd *tfd)
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+{
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+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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+ int i, num_tbs;
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+
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+ /* Sanity check on number of chunks */
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+ num_tbs = iwl_pcie_gen2_get_num_tbs(trans, tfd);
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+
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+ if (num_tbs >= trans_pcie->max_tbs) {
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+ IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
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+ return;
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+ }
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+
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+ /* first TB is never freed - it's the bidirectional DMA data */
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+ for (i = 1; i < num_tbs; i++) {
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+ if (meta->tbs & BIT(i))
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+ dma_unmap_page(trans->dev,
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+ le64_to_cpu(tfd->tbs[i].addr),
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+ le16_to_cpu(tfd->tbs[i].tb_len),
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+ DMA_TO_DEVICE);
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+ else
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+ dma_unmap_single(trans->dev,
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+ le64_to_cpu(tfd->tbs[i].addr),
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+ le16_to_cpu(tfd->tbs[i].tb_len),
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+ DMA_TO_DEVICE);
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+ }
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+
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+ tfd->num_tbs = 0;
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+}
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+
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+static void iwl_pcie_gen2_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
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+{
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+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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+
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+ /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
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+ * idx is bounded by n_window
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+ */
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+ int rd_ptr = txq->read_ptr;
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+ int idx = get_cmd_index(txq, rd_ptr);
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+
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+ lockdep_assert_held(&txq->lock);
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+
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+ /* We have only q->n_window txq->entries, but we use
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+ * TFD_QUEUE_SIZE_MAX tfds
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+ */
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+ iwl_pcie_gen2_tfd_unmap(trans, &txq->entries[idx].meta,
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+ iwl_pcie_get_tfd(trans_pcie, txq, rd_ptr));
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+
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+ /* free SKB */
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+ if (txq->entries) {
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+ struct sk_buff *skb;
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+
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+ skb = txq->entries[idx].skb;
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+
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+ /* Can be called from irqs-disabled context
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+ * If skb is not NULL, it means that the whole queue is being
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+ * freed and that the queue is not empty - free the skb
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+ */
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+ if (skb) {
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+ iwl_op_mode_free_skb(trans->op_mode, skb);
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+ txq->entries[idx].skb = NULL;
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+ }
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+ }
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+}
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+
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+static int iwl_pcie_gen2_set_tb(struct iwl_trans *trans,
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+ struct iwl_tfh_tfd *tfd, dma_addr_t addr,
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+ u16 len)
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+{
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+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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+ int idx = iwl_pcie_gen2_get_num_tbs(trans, tfd);
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+ struct iwl_tfh_tb *tb = &tfd->tbs[idx];
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+
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+ /* Each TFD can point to a maximum max_tbs Tx buffers */
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+ if (le16_to_cpu(tfd->num_tbs) >= trans_pcie->max_tbs) {
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+ IWL_ERR(trans, "Error can not send more than %d chunks\n",
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+ trans_pcie->max_tbs);
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+ return -EINVAL;
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+ }
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+
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+ put_unaligned_le64(addr, &tb->addr);
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+ tb->tb_len = cpu_to_le16(len);
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+
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+ tfd->num_tbs = cpu_to_le16(idx + 1);
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+
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+ return idx;
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+}
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+
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+static
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+struct iwl_tfh_tfd *iwl_pcie_gen2_build_tfd(struct iwl_trans *trans,
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+ struct iwl_txq *txq,
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+ struct iwl_device_cmd *dev_cmd,
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+ struct sk_buff *skb,
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+ struct iwl_cmd_meta *out_meta)
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+{
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+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
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+ struct iwl_tfh_tfd *tfd =
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+ iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr);
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+ dma_addr_t tb_phys;
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+ int i, len, tb1_len, tb2_len, hdr_len;
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+ void *tb1_addr;
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+
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+ memset(tfd, 0, sizeof(*tfd));
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+
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+ tb_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr);
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+ /* The first TB points to bi-directional DMA data */
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+ memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr,
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+ IWL_FIRST_TB_SIZE);
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+
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+ iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, IWL_FIRST_TB_SIZE);
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+
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+ /* there must be data left over for TB1 or this code must be changed */
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+ BUILD_BUG_ON(sizeof(struct iwl_tx_cmd_gen2) < IWL_FIRST_TB_SIZE);
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+
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+ /*
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+ * The second TB (tb1) points to the remainder of the TX command
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+ * and the 802.11 header - dword aligned size
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+ * (This calculation modifies the TX command, so do it before the
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+ * setup of the first TB)
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+ */
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+ len = sizeof(struct iwl_tx_cmd_gen2) + sizeof(struct iwl_cmd_header) +
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+ ieee80211_hdrlen(hdr->frame_control) - IWL_FIRST_TB_SIZE;
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+
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+ tb1_len = ALIGN(len, 4);
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+
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+ /* map the data for TB1 */
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+ tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
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+ tb_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
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+ if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
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+ goto out_err;
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+ iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb1_len);
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+
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+ /* set up TFD's third entry to point to remainder of skb's head */
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+ hdr_len = ieee80211_hdrlen(hdr->frame_control);
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+ tb2_len = skb_headlen(skb) - hdr_len;
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+
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+ if (tb2_len > 0) {
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+ tb_phys = dma_map_single(trans->dev, skb->data + hdr_len,
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+ tb2_len, DMA_TO_DEVICE);
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+ if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
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+ goto out_err;
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+ iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb2_len);
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+ }
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+
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+ /* set up the remaining entries to point to the data */
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+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
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+ const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
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+ int tb_idx;
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+
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+ if (!skb_frag_size(frag))
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+ continue;
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+
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+ tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
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+ skb_frag_size(frag), DMA_TO_DEVICE);
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+
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+ if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
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+ goto out_err;
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+ tb_idx = iwl_pcie_gen2_set_tb(trans, tfd, tb_phys,
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+ skb_frag_size(frag));
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+
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+ out_meta->tbs |= BIT(tb_idx);
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+ }
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+
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+ trace_iwlwifi_dev_tx(trans->dev, skb, tfd, sizeof(*tfd), &dev_cmd->hdr,
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+ IWL_FIRST_TB_SIZE + tb1_len,
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+ skb->data + hdr_len, tb2_len);
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+ trace_iwlwifi_dev_tx_data(trans->dev, skb, hdr_len,
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+ skb->len - hdr_len);
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+
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+ return tfd;
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+
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+out_err:
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+ iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
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+ return NULL;
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+}
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+
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+int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
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+ struct iwl_device_cmd *dev_cmd, int txq_id)
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+{
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+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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+ struct iwl_tx_cmd_gen2 *tx_cmd = (void *)dev_cmd->payload;
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+ struct iwl_cmd_meta *out_meta;
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+ struct iwl_txq *txq = trans_pcie->txq[txq_id];
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+ void *tfd;
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+
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+ if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
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+ "TX on unused queue %d\n", txq_id))
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+ return -EINVAL;
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+
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+ if (skb_is_nonlinear(skb) &&
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+ skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
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+ __skb_linearize(skb))
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+ return -ENOMEM;
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+
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+ spin_lock(&txq->lock);
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+
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+ /* Set up driver data for this TFD */
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+ txq->entries[txq->write_ptr].skb = skb;
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+ txq->entries[txq->write_ptr].cmd = dev_cmd;
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+
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+ dev_cmd->hdr.sequence =
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+ cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
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+ INDEX_TO_SEQ(txq->write_ptr)));
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+
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+ /* Set up first empty entry in queue's array of Tx/cmd buffers */
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+ out_meta = &txq->entries[txq->write_ptr].meta;
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+ out_meta->flags = 0;
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+
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+ tfd = iwl_pcie_gen2_build_tfd(trans, txq, dev_cmd, skb, out_meta);
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+ if (!tfd) {
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+ spin_unlock(&txq->lock);
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+ return -1;
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+ }
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+
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+ /* Set up entry for this TFD in Tx byte-count array */
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+ iwl_pcie_gen2_update_byte_tbl(txq, le16_to_cpu(tx_cmd->len),
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|
|
+ iwl_pcie_gen2_get_num_tbs(trans, tfd));
|
|
|
+
|
|
|
+ /* start timer if queue currently empty */
|
|
|
+ if (txq->read_ptr == txq->write_ptr) {
|
|
|
+ if (txq->wd_timeout)
|
|
|
+ mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
|
|
|
+ IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id);
|
|
|
+ iwl_trans_ref(trans);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Tell device the write index *just past* this latest filled TFD */
|
|
|
+ txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr);
|
|
|
+ iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq);
|
|
|
+ if (iwl_queue_space(txq) < txq->high_mark)
|
|
|
+ iwl_stop_queue(trans, txq);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * At this point the frame is "transmitted" successfully
|
|
|
+ * and we will get a TX status notification eventually.
|
|
|
+ */
|
|
|
+ spin_unlock(&txq->lock);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/*************** HOST COMMAND QUEUE FUNCTIONS *****/
|
|
|
+
|
|
|
+/*
|
|
|
+ * iwl_pcie_gen2_enqueue_hcmd - enqueue a uCode command
|
|
|
+ * @priv: device private data point
|
|
|
+ * @cmd: a pointer to the ucode command structure
|
|
|
+ *
|
|
|
+ * The function returns < 0 values to indicate the operation
|
|
|
+ * failed. On success, it returns the index (>= 0) of command in the
|
|
|
+ * command queue.
|
|
|
+ */
|
|
|
+static int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
|
|
|
+ struct iwl_host_cmd *cmd)
|
|
|
+{
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
+ struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
|
|
|
+ struct iwl_device_cmd *out_cmd;
|
|
|
+ struct iwl_cmd_meta *out_meta;
|
|
|
+ unsigned long flags;
|
|
|
+ void *dup_buf = NULL;
|
|
|
+ dma_addr_t phys_addr;
|
|
|
+ int idx, i, cmd_pos;
|
|
|
+ u16 copy_size, cmd_size, tb0_size;
|
|
|
+ bool had_nocopy = false;
|
|
|
+ u8 group_id = iwl_cmd_groupid(cmd->id);
|
|
|
+ const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
|
|
|
+ u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
|
|
|
+ struct iwl_tfh_tfd *tfd =
|
|
|
+ iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr);
|
|
|
+
|
|
|
+ memset(tfd, 0, sizeof(*tfd));
|
|
|
+
|
|
|
+ copy_size = sizeof(struct iwl_cmd_header_wide);
|
|
|
+ cmd_size = sizeof(struct iwl_cmd_header_wide);
|
|
|
+
|
|
|
+ for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
|
|
|
+ cmddata[i] = cmd->data[i];
|
|
|
+ cmdlen[i] = cmd->len[i];
|
|
|
+
|
|
|
+ if (!cmd->len[i])
|
|
|
+ continue;
|
|
|
+
|
|
|
+ /* need at least IWL_FIRST_TB_SIZE copied */
|
|
|
+ if (copy_size < IWL_FIRST_TB_SIZE) {
|
|
|
+ int copy = IWL_FIRST_TB_SIZE - copy_size;
|
|
|
+
|
|
|
+ if (copy > cmdlen[i])
|
|
|
+ copy = cmdlen[i];
|
|
|
+ cmdlen[i] -= copy;
|
|
|
+ cmddata[i] += copy;
|
|
|
+ copy_size += copy;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
|
|
|
+ had_nocopy = true;
|
|
|
+ if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
|
|
|
+ idx = -EINVAL;
|
|
|
+ goto free_dup_buf;
|
|
|
+ }
|
|
|
+ } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
|
|
|
+ /*
|
|
|
+ * This is also a chunk that isn't copied
|
|
|
+ * to the static buffer so set had_nocopy.
|
|
|
+ */
|
|
|
+ had_nocopy = true;
|
|
|
+
|
|
|
+ /* only allowed once */
|
|
|
+ if (WARN_ON(dup_buf)) {
|
|
|
+ idx = -EINVAL;
|
|
|
+ goto free_dup_buf;
|
|
|
+ }
|
|
|
+
|
|
|
+ dup_buf = kmemdup(cmddata[i], cmdlen[i],
|
|
|
+ GFP_ATOMIC);
|
|
|
+ if (!dup_buf)
|
|
|
+ return -ENOMEM;
|
|
|
+ } else {
|
|
|
+ /* NOCOPY must not be followed by normal! */
|
|
|
+ if (WARN_ON(had_nocopy)) {
|
|
|
+ idx = -EINVAL;
|
|
|
+ goto free_dup_buf;
|
|
|
+ }
|
|
|
+ copy_size += cmdlen[i];
|
|
|
+ }
|
|
|
+ cmd_size += cmd->len[i];
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * If any of the command structures end up being larger than the
|
|
|
+ * TFD_MAX_PAYLOAD_SIZE and they aren't dynamically allocated into
|
|
|
+ * separate TFDs, then we will need to increase the size of the buffers
|
|
|
+ */
|
|
|
+ if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
|
|
|
+ "Command %s (%#x) is too large (%d bytes)\n",
|
|
|
+ iwl_get_cmd_string(trans, cmd->id), cmd->id, copy_size)) {
|
|
|
+ idx = -EINVAL;
|
|
|
+ goto free_dup_buf;
|
|
|
+ }
|
|
|
+
|
|
|
+ spin_lock_bh(&txq->lock);
|
|
|
+
|
|
|
+ if (iwl_queue_space(txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
|
|
|
+ spin_unlock_bh(&txq->lock);
|
|
|
+
|
|
|
+ IWL_ERR(trans, "No space in command queue\n");
|
|
|
+ iwl_op_mode_cmd_queue_full(trans->op_mode);
|
|
|
+ idx = -ENOSPC;
|
|
|
+ goto free_dup_buf;
|
|
|
+ }
|
|
|
+
|
|
|
+ idx = get_cmd_index(txq, txq->write_ptr);
|
|
|
+ out_cmd = txq->entries[idx].cmd;
|
|
|
+ out_meta = &txq->entries[idx].meta;
|
|
|
+
|
|
|
+ /* re-initialize to NULL */
|
|
|
+ memset(out_meta, 0, sizeof(*out_meta));
|
|
|
+ if (cmd->flags & CMD_WANT_SKB)
|
|
|
+ out_meta->source = cmd;
|
|
|
+
|
|
|
+ /* set up the header */
|
|
|
+ out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
|
|
|
+ out_cmd->hdr_wide.group_id = group_id;
|
|
|
+ out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
|
|
|
+ out_cmd->hdr_wide.length =
|
|
|
+ cpu_to_le16(cmd_size - sizeof(struct iwl_cmd_header_wide));
|
|
|
+ out_cmd->hdr_wide.reserved = 0;
|
|
|
+ out_cmd->hdr_wide.sequence =
|
|
|
+ cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
|
|
|
+ INDEX_TO_SEQ(txq->write_ptr));
|
|
|
+
|
|
|
+ cmd_pos = sizeof(struct iwl_cmd_header_wide);
|
|
|
+ copy_size = sizeof(struct iwl_cmd_header_wide);
|
|
|
+
|
|
|
+ /* and copy the data that needs to be copied */
|
|
|
+ for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
|
|
|
+ int copy;
|
|
|
+
|
|
|
+ if (!cmd->len[i])
|
|
|
+ continue;
|
|
|
+
|
|
|
+ /* copy everything if not nocopy/dup */
|
|
|
+ if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
|
|
|
+ IWL_HCMD_DFL_DUP))) {
|
|
|
+ copy = cmd->len[i];
|
|
|
+
|
|
|
+ memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
|
|
|
+ cmd_pos += copy;
|
|
|
+ copy_size += copy;
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Otherwise we need at least IWL_FIRST_TB_SIZE copied
|
|
|
+ * in total (for bi-directional DMA), but copy up to what
|
|
|
+ * we can fit into the payload for debug dump purposes.
|
|
|
+ */
|
|
|
+ copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
|
|
|
+
|
|
|
+ memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
|
|
|
+ cmd_pos += copy;
|
|
|
+
|
|
|
+ /* However, treat copy_size the proper way, we need it below */
|
|
|
+ if (copy_size < IWL_FIRST_TB_SIZE) {
|
|
|
+ copy = IWL_FIRST_TB_SIZE - copy_size;
|
|
|
+
|
|
|
+ if (copy > cmd->len[i])
|
|
|
+ copy = cmd->len[i];
|
|
|
+ copy_size += copy;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ IWL_DEBUG_HC(trans,
|
|
|
+ "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
|
|
|
+ iwl_get_cmd_string(trans, cmd->id), group_id,
|
|
|
+ out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
|
|
|
+ cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
|
|
|
+
|
|
|
+ /* start the TFD with the minimum copy bytes */
|
|
|
+ tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
|
|
|
+ memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
|
|
|
+ iwl_pcie_gen2_set_tb(trans, tfd, iwl_pcie_get_first_tb_dma(txq, idx),
|
|
|
+ tb0_size);
|
|
|
+
|
|
|
+ /* map first command fragment, if any remains */
|
|
|
+ if (copy_size > tb0_size) {
|
|
|
+ phys_addr = dma_map_single(trans->dev,
|
|
|
+ ((u8 *)&out_cmd->hdr) + tb0_size,
|
|
|
+ copy_size - tb0_size,
|
|
|
+ DMA_TO_DEVICE);
|
|
|
+ if (dma_mapping_error(trans->dev, phys_addr)) {
|
|
|
+ idx = -ENOMEM;
|
|
|
+ iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+ iwl_pcie_gen2_set_tb(trans, tfd, phys_addr,
|
|
|
+ copy_size - tb0_size);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* map the remaining (adjusted) nocopy/dup fragments */
|
|
|
+ for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
|
|
|
+ const void *data = cmddata[i];
|
|
|
+
|
|
|
+ if (!cmdlen[i])
|
|
|
+ continue;
|
|
|
+ if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
|
|
|
+ IWL_HCMD_DFL_DUP)))
|
|
|
+ continue;
|
|
|
+ if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
|
|
|
+ data = dup_buf;
|
|
|
+ phys_addr = dma_map_single(trans->dev, (void *)data,
|
|
|
+ cmdlen[i], DMA_TO_DEVICE);
|
|
|
+ if (dma_mapping_error(trans->dev, phys_addr)) {
|
|
|
+ idx = -ENOMEM;
|
|
|
+ iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd);
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+ iwl_pcie_gen2_set_tb(trans, tfd, phys_addr, cmdlen[i]);
|
|
|
+ }
|
|
|
+
|
|
|
+ BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
|
|
|
+ out_meta->flags = cmd->flags;
|
|
|
+ if (WARN_ON_ONCE(txq->entries[idx].free_buf))
|
|
|
+ kzfree(txq->entries[idx].free_buf);
|
|
|
+ txq->entries[idx].free_buf = dup_buf;
|
|
|
+
|
|
|
+ trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
|
|
|
+
|
|
|
+ /* start timer if queue currently empty */
|
|
|
+ if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
|
|
|
+ mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
|
|
|
+
|
|
|
+ spin_lock_irqsave(&trans_pcie->reg_lock, flags);
|
|
|
+ if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
|
|
|
+ !trans_pcie->ref_cmd_in_flight) {
|
|
|
+ trans_pcie->ref_cmd_in_flight = true;
|
|
|
+ IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
|
|
|
+ iwl_trans_ref(trans);
|
|
|
+ }
|
|
|
+ /* Increment and update queue's write index */
|
|
|
+ txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr);
|
|
|
+ iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq);
|
|
|
+ spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
|
|
|
+
|
|
|
+out:
|
|
|
+ spin_unlock_bh(&txq->lock);
|
|
|
+free_dup_buf:
|
|
|
+ if (idx < 0)
|
|
|
+ kfree(dup_buf);
|
|
|
+ return idx;
|
|
|
+}
|
|
|
+
|
|
|
+#define HOST_COMPLETE_TIMEOUT (2 * HZ)
|
|
|
+
|
|
|
+static int iwl_pcie_gen2_send_hcmd_sync(struct iwl_trans *trans,
|
|
|
+ struct iwl_host_cmd *cmd)
|
|
|
+{
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
+ const char *cmd_str = iwl_get_cmd_string(trans, cmd->id);
|
|
|
+ struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
|
|
|
+ int cmd_idx;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", cmd_str);
|
|
|
+
|
|
|
+ if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
|
|
|
+ &trans->status),
|
|
|
+ "Command %s: a command is already active!\n", cmd_str))
|
|
|
+ return -EIO;
|
|
|
+
|
|
|
+ IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", cmd_str);
|
|
|
+
|
|
|
+ if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) {
|
|
|
+ ret = wait_event_timeout(trans_pcie->d0i3_waitq,
|
|
|
+ pm_runtime_active(&trans_pcie->pci_dev->dev),
|
|
|
+ msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT));
|
|
|
+ if (!ret) {
|
|
|
+ IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n");
|
|
|
+ return -ETIMEDOUT;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ cmd_idx = iwl_pcie_gen2_enqueue_hcmd(trans, cmd);
|
|
|
+ if (cmd_idx < 0) {
|
|
|
+ ret = cmd_idx;
|
|
|
+ clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
|
|
|
+ IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
|
|
|
+ cmd_str, ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = wait_event_timeout(trans_pcie->wait_command_queue,
|
|
|
+ !test_bit(STATUS_SYNC_HCMD_ACTIVE,
|
|
|
+ &trans->status),
|
|
|
+ HOST_COMPLETE_TIMEOUT);
|
|
|
+ if (!ret) {
|
|
|
+ IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
|
|
|
+ cmd_str, jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
|
|
|
+
|
|
|
+ IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
|
|
|
+ txq->read_ptr, txq->write_ptr);
|
|
|
+
|
|
|
+ clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
|
|
|
+ IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
|
|
|
+ cmd_str);
|
|
|
+ ret = -ETIMEDOUT;
|
|
|
+
|
|
|
+ iwl_force_nmi(trans);
|
|
|
+ iwl_trans_fw_error(trans);
|
|
|
+
|
|
|
+ goto cancel;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (test_bit(STATUS_FW_ERROR, &trans->status)) {
|
|
|
+ IWL_ERR(trans, "FW error in SYNC CMD %s\n", cmd_str);
|
|
|
+ dump_stack();
|
|
|
+ ret = -EIO;
|
|
|
+ goto cancel;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
|
|
|
+ test_bit(STATUS_RFKILL, &trans->status)) {
|
|
|
+ IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
|
|
|
+ ret = -ERFKILL;
|
|
|
+ goto cancel;
|
|
|
+ }
|
|
|
+
|
|
|
+ if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
|
|
|
+ IWL_ERR(trans, "Error: Response NULL in '%s'\n", cmd_str);
|
|
|
+ ret = -EIO;
|
|
|
+ goto cancel;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+cancel:
|
|
|
+ if (cmd->flags & CMD_WANT_SKB) {
|
|
|
+ /*
|
|
|
+ * Cancel the CMD_WANT_SKB flag for the cmd in the
|
|
|
+ * TX cmd queue. Otherwise in case the cmd comes
|
|
|
+ * in later, it will possibly set an invalid
|
|
|
+ * address (cmd->meta.source).
|
|
|
+ */
|
|
|
+ txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (cmd->resp_pkt) {
|
|
|
+ iwl_free_resp(cmd);
|
|
|
+ cmd->resp_pkt = NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
|
|
|
+ struct iwl_host_cmd *cmd)
|
|
|
+{
|
|
|
+ if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
|
|
|
+ test_bit(STATUS_RFKILL, &trans->status)) {
|
|
|
+ IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
|
|
|
+ cmd->id);
|
|
|
+ return -ERFKILL;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (cmd->flags & CMD_ASYNC) {
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ /* An asynchronous command can not expect an SKB to be set. */
|
|
|
+ if (WARN_ON(cmd->flags & CMD_WANT_SKB))
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ ret = iwl_pcie_gen2_enqueue_hcmd(trans, cmd);
|
|
|
+ if (ret < 0) {
|
|
|
+ IWL_ERR(trans,
|
|
|
+ "Error sending %s: enqueue_hcmd failed: %d\n",
|
|
|
+ iwl_get_cmd_string(trans, cmd->id), ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ return iwl_pcie_gen2_send_hcmd_sync(trans, cmd);
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * iwl_pcie_gen2_txq_unmap - Unmap any remaining DMA mappings and free skb's
|
|
|
+ */
|
|
|
+void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id)
|
|
|
+{
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
+ struct iwl_txq *txq = trans_pcie->txq[txq_id];
|
|
|
+
|
|
|
+ spin_lock_bh(&txq->lock);
|
|
|
+ while (txq->write_ptr != txq->read_ptr) {
|
|
|
+ IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
|
|
|
+ txq_id, txq->read_ptr);
|
|
|
+
|
|
|
+ iwl_pcie_gen2_free_tfd(trans, txq);
|
|
|
+ txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr);
|
|
|
+
|
|
|
+ if (txq->read_ptr == txq->write_ptr) {
|
|
|
+ unsigned long flags;
|
|
|
+
|
|
|
+ spin_lock_irqsave(&trans_pcie->reg_lock, flags);
|
|
|
+ if (txq_id != trans_pcie->cmd_queue) {
|
|
|
+ IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n",
|
|
|
+ txq->id);
|
|
|
+ iwl_trans_unref(trans);
|
|
|
+ } else if (trans_pcie->ref_cmd_in_flight) {
|
|
|
+ trans_pcie->ref_cmd_in_flight = false;
|
|
|
+ IWL_DEBUG_RPM(trans,
|
|
|
+ "clear ref_cmd_in_flight\n");
|
|
|
+ iwl_trans_unref(trans);
|
|
|
+ }
|
|
|
+ spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ spin_unlock_bh(&txq->lock);
|
|
|
+
|
|
|
+ /* just in case - this queue may have been stopped */
|
|
|
+ iwl_wake_queue(trans, txq);
|
|
|
+}
|
|
|
+
|
|
|
+static void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans,
|
|
|
+ struct iwl_txq *txq)
|
|
|
+{
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
+ struct device *dev = trans->dev;
|
|
|
+
|
|
|
+ /* De-alloc circular buffer of TFDs */
|
|
|
+ if (txq->tfds) {
|
|
|
+ dma_free_coherent(dev,
|
|
|
+ trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX,
|
|
|
+ txq->tfds, txq->dma_addr);
|
|
|
+ dma_free_coherent(dev,
|
|
|
+ sizeof(*txq->first_tb_bufs) * txq->n_window,
|
|
|
+ txq->first_tb_bufs, txq->first_tb_dma);
|
|
|
+ }
|
|
|
+
|
|
|
+ kfree(txq->entries);
|
|
|
+ iwl_pcie_free_dma_ptr(trans, &txq->bc_tbl);
|
|
|
+ kfree(txq);
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * iwl_pcie_txq_free - Deallocate DMA queue.
|
|
|
+ * @txq: Transmit queue to deallocate.
|
|
|
+ *
|
|
|
+ * Empty queue by removing and destroying all BD's.
|
|
|
+ * Free all buffers.
|
|
|
+ * 0-fill, but do not free "txq" descriptor structure.
|
|
|
+ */
|
|
|
+static void iwl_pcie_gen2_txq_free(struct iwl_trans *trans, int txq_id)
|
|
|
+{
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
+ struct iwl_txq *txq = trans_pcie->txq[txq_id];
|
|
|
+ int i;
|
|
|
+
|
|
|
+ if (WARN_ON(!txq))
|
|
|
+ return;
|
|
|
+
|
|
|
+ iwl_pcie_gen2_txq_unmap(trans, txq_id);
|
|
|
+
|
|
|
+ /* De-alloc array of command/tx buffers */
|
|
|
+ if (txq_id == trans_pcie->cmd_queue)
|
|
|
+ for (i = 0; i < txq->n_window; i++) {
|
|
|
+ kzfree(txq->entries[i].cmd);
|
|
|
+ kzfree(txq->entries[i].free_buf);
|
|
|
+ }
|
|
|
+ del_timer_sync(&txq->stuck_timer);
|
|
|
+
|
|
|
+ iwl_pcie_gen2_txq_free_memory(trans, txq);
|
|
|
+
|
|
|
+ trans_pcie->txq[txq_id] = NULL;
|
|
|
+
|
|
|
+ clear_bit(txq_id, trans_pcie->queue_used);
|
|
|
+}
|
|
|
+
|
|
|
+int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans,
|
|
|
+ struct iwl_tx_queue_cfg_cmd *cmd,
|
|
|
+ int cmd_id,
|
|
|
+ unsigned int timeout)
|
|
|
+{
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
+ struct iwl_tx_queue_cfg_rsp *rsp;
|
|
|
+ struct iwl_txq *txq;
|
|
|
+ struct iwl_host_cmd hcmd = {
|
|
|
+ .id = cmd_id,
|
|
|
+ .len = { sizeof(*cmd) },
|
|
|
+ .data = { cmd, },
|
|
|
+ .flags = CMD_WANT_SKB,
|
|
|
+ };
|
|
|
+ int ret, qid;
|
|
|
+
|
|
|
+ txq = kzalloc(sizeof(*txq), GFP_KERNEL);
|
|
|
+ if (!txq)
|
|
|
+ return -ENOMEM;
|
|
|
+ ret = iwl_pcie_alloc_dma_ptr(trans, &txq->bc_tbl,
|
|
|
+ sizeof(struct iwlagn_scd_bc_tbl));
|
|
|
+ if (ret) {
|
|
|
+ IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
|
|
|
+ kfree(txq);
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = iwl_pcie_txq_alloc(trans, txq, TFD_TX_CMD_SLOTS, false);
|
|
|
+ if (ret) {
|
|
|
+ IWL_ERR(trans, "Tx queue alloc failed\n");
|
|
|
+ goto error;
|
|
|
+ }
|
|
|
+ ret = iwl_pcie_txq_init(trans, txq, TFD_TX_CMD_SLOTS, false);
|
|
|
+ if (ret) {
|
|
|
+ IWL_ERR(trans, "Tx queue init failed\n");
|
|
|
+ goto error;
|
|
|
+ }
|
|
|
+
|
|
|
+ txq->wd_timeout = msecs_to_jiffies(timeout);
|
|
|
+
|
|
|
+ cmd->tfdq_addr = cpu_to_le64(txq->dma_addr);
|
|
|
+ cmd->byte_cnt_addr = cpu_to_le64(txq->bc_tbl.dma);
|
|
|
+ cmd->cb_size = cpu_to_le32(TFD_QUEUE_CB_SIZE(TFD_QUEUE_SIZE_MAX));
|
|
|
+
|
|
|
+ ret = iwl_trans_send_cmd(trans, &hcmd);
|
|
|
+ if (ret)
|
|
|
+ goto error;
|
|
|
+
|
|
|
+ if (WARN_ON(iwl_rx_packet_payload_len(hcmd.resp_pkt) != sizeof(*rsp))) {
|
|
|
+ ret = -EINVAL;
|
|
|
+ goto error;
|
|
|
+ }
|
|
|
+
|
|
|
+ rsp = (void *)hcmd.resp_pkt->data;
|
|
|
+ qid = le16_to_cpu(rsp->queue_number);
|
|
|
+
|
|
|
+ if (qid > ARRAY_SIZE(trans_pcie->txq)) {
|
|
|
+ WARN_ONCE(1, "queue index %d unsupported", qid);
|
|
|
+ ret = -EIO;
|
|
|
+ goto error;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (test_and_set_bit(qid, trans_pcie->queue_used)) {
|
|
|
+ WARN_ONCE(1, "queue %d already used", qid);
|
|
|
+ ret = -EIO;
|
|
|
+ goto error;
|
|
|
+ }
|
|
|
+
|
|
|
+ txq->id = qid;
|
|
|
+ trans_pcie->txq[qid] = txq;
|
|
|
+
|
|
|
+ /* Place first TFD at index corresponding to start sequence number */
|
|
|
+ txq->read_ptr = le16_to_cpu(rsp->write_pointer);
|
|
|
+ txq->write_ptr = le16_to_cpu(rsp->write_pointer);
|
|
|
+ iwl_write_direct32(trans, HBUS_TARG_WRPTR,
|
|
|
+ (txq->write_ptr) | (qid << 16));
|
|
|
+ IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d\n", qid);
|
|
|
+
|
|
|
+ return qid;
|
|
|
+
|
|
|
+error:
|
|
|
+ iwl_pcie_gen2_txq_free_memory(trans, txq);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue)
|
|
|
+{
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Upon HW Rfkill - we stop the device, and then stop the queues
|
|
|
+ * in the op_mode. Just for the sake of the simplicity of the op_mode,
|
|
|
+ * allow the op_mode to call txq_disable after it already called
|
|
|
+ * stop_device.
|
|
|
+ */
|
|
|
+ if (!test_and_clear_bit(queue, trans_pcie->queue_used)) {
|
|
|
+ WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
|
|
|
+ "queue %d not used", queue);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ iwl_pcie_gen2_txq_unmap(trans, queue);
|
|
|
+
|
|
|
+ IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", queue);
|
|
|
+}
|
|
|
+
|
|
|
+void iwl_pcie_gen2_tx_free(struct iwl_trans *trans)
|
|
|
+{
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
+ int i;
|
|
|
+
|
|
|
+ memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
|
|
|
+
|
|
|
+ /* Free all TX queues */
|
|
|
+ for (i = 0; i < ARRAY_SIZE(trans_pcie->txq); i++) {
|
|
|
+ if (!trans_pcie->txq[i])
|
|
|
+ continue;
|
|
|
+
|
|
|
+ iwl_pcie_gen2_txq_free(trans, i);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+int iwl_pcie_gen2_tx_init(struct iwl_trans *trans)
|
|
|
+{
|
|
|
+ struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
+ struct iwl_txq *cmd_queue;
|
|
|
+ int txq_id = trans_pcie->cmd_queue, ret;
|
|
|
+
|
|
|
+ /* alloc and init the command queue */
|
|
|
+ if (!trans_pcie->txq[txq_id]) {
|
|
|
+ cmd_queue = kzalloc(sizeof(*cmd_queue), GFP_KERNEL);
|
|
|
+ if (!cmd_queue) {
|
|
|
+ IWL_ERR(trans, "Not enough memory for command queue\n");
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+ trans_pcie->txq[txq_id] = cmd_queue;
|
|
|
+ ret = iwl_pcie_txq_alloc(trans, cmd_queue, TFD_CMD_SLOTS, true);
|
|
|
+ if (ret) {
|
|
|
+ IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
|
|
|
+ goto error;
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ cmd_queue = trans_pcie->txq[txq_id];
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = iwl_pcie_txq_init(trans, cmd_queue, TFD_CMD_SLOTS, true);
|
|
|
+ if (ret) {
|
|
|
+ IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
|
|
|
+ goto error;
|
|
|
+ }
|
|
|
+ trans_pcie->txq[txq_id]->id = txq_id;
|
|
|
+ set_bit(txq_id, trans_pcie->queue_used);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+error:
|
|
|
+ iwl_pcie_gen2_tx_free(trans);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|