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x86/cpufeature: Move processor tracing out of scattered features

Processor tracing is already enumerated in word 9 (CPUID[7,0].EBX),
so do not duplicate it in the scattered features word.

Besides being more tidy, this will be useful for KVM when it presents
processor tracing to the guests.  KVM selects host features that are
supported by both the host kernel (depending on command line options,
CPU errata, or whatever) and KVM.  Whenever a full feature word exists,
KVM's code is written in the expectation that the CPUID bit number
matches the X86_FEATURE_* bit number, but this is not the case for
X86_FEATURE_INTEL_PT.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Luwei Kang <luwei.kang@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: kvm@vger.kernel.org
Link: http://lkml.kernel.org/r/1516117345-34561-1-git-send-email-pbonzini@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Paolo Bonzini 7 years ago
parent
385d11b152
commit
4fdec2034b
2 changed files with 1 additions and 2 deletions
Split View Show Diff Stats
  1. 1 1
      arch/x86/include/asm/cpufeatures.h
  2. 0 1
      arch/x86/kernel/cpu/scattered.c

+ 1 - 1
arch/x86/include/asm/cpufeatures.h
View File 

@@ -206,7 +206,6 @@
 
 #define X86_FEATURE_RETPOLINE		( 7*32+12) /* Generic Retpoline mitigation for Spectre variant 2 */
 
 #define X86_FEATURE_RETPOLINE_AMD	( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */
 
 #define X86_FEATURE_INTEL_PPIN		( 7*32+14) /* Intel Processor Inventory Number */
 
-#define X86_FEATURE_INTEL_PT		( 7*32+15) /* Intel Processor Trace */
 
 #define X86_FEATURE_AVX512_4VNNIW	( 7*32+16) /* AVX-512 Neural Network Instructions */
 
 #define X86_FEATURE_AVX512_4FMAPS	( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */
 
 
@@ -246,6 +245,7 @@
 
 #define X86_FEATURE_AVX512IFMA		( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
 
 #define X86_FEATURE_CLFLUSHOPT		( 9*32+23) /* CLFLUSHOPT instruction */
 
 #define X86_FEATURE_CLWB		( 9*32+24) /* CLWB instruction */
 
+#define X86_FEATURE_INTEL_PT		( 9*32+25) /* Intel Processor Trace */
 
 #define X86_FEATURE_AVX512PF		( 9*32+26) /* AVX-512 Prefetch */
 
 #define X86_FEATURE_AVX512ER		( 9*32+27) /* AVX-512 Exponential and Reciprocal */
 
 #define X86_FEATURE_AVX512CD		( 9*32+28) /* AVX-512 Conflict Detection */

+ 0 - 1
arch/x86/kernel/cpu/scattered.c
View File 

@@ -21,7 +21,6 @@ struct cpuid_bit {
 
 static const struct cpuid_bit cpuid_bits[] = {
 
 	{ X86_FEATURE_APERFMPERF,       CPUID_ECX,  0, 0x00000006, 0 },
 
 	{ X86_FEATURE_EPB,		CPUID_ECX,  3, 0x00000006, 0 },
 
-	{ X86_FEATURE_INTEL_PT,		CPUID_EBX, 25, 0x00000007, 0 },
 
 	{ X86_FEATURE_AVX512_4VNNIW,    CPUID_EDX,  2, 0x00000007, 0 },
 
 	{ X86_FEATURE_AVX512_4FMAPS,    CPUID_EDX,  3, 0x00000007, 0 },
 
 	{ X86_FEATURE_CAT_L3,		CPUID_EBX,  1, 0x00000010, 0 },