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@@ -42,7 +42,7 @@
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#define NSS_COMMON_CLK_DIV_MASK 0x7f
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#define NSS_COMMON_CLK_DIV_MASK 0x7f
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#define NSS_COMMON_CLK_SRC_CTRL 0x14
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#define NSS_COMMON_CLK_SRC_CTRL 0x14
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-#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (1 << x)
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+#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (x)
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/* Mode is coded on 1 bit but is different depending on the MAC ID:
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/* Mode is coded on 1 bit but is different depending on the MAC ID:
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* MAC0: QSGMII=0 RGMII=1
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* MAC0: QSGMII=0 RGMII=1
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* MAC1: QSGMII=0 SGMII=0 RGMII=1
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* MAC1: QSGMII=0 SGMII=0 RGMII=1
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@@ -291,7 +291,7 @@ static void *ipq806x_gmac_setup(struct platform_device *pdev)
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/* Configure the clock src according to the mode */
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/* Configure the clock src according to the mode */
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regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val);
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regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val);
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- val &= ~NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
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+ val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id));
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switch (gmac->phy_mode) {
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switch (gmac->phy_mode) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII:
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val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<
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val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<
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