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@@ -823,6 +823,60 @@ static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
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},
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};
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+static const struct amdgpu_ip_block_version topaz_ip_blocks_vd[] =
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+{
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+ /* ORDER MATTERS! */
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+ {
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+ .type = AMD_IP_BLOCK_TYPE_COMMON,
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+ .major = 2,
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+ .minor = 0,
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+ .rev = 0,
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+ .funcs = &vi_common_ip_funcs,
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+ },
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+ {
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+ .type = AMD_IP_BLOCK_TYPE_GMC,
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+ .major = 7,
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+ .minor = 4,
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+ .rev = 0,
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+ .funcs = &gmc_v7_0_ip_funcs,
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+ },
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+ {
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+ .type = AMD_IP_BLOCK_TYPE_IH,
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+ .major = 2,
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+ .minor = 4,
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+ .rev = 0,
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+ .funcs = &iceland_ih_ip_funcs,
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+ },
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+ {
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+ .type = AMD_IP_BLOCK_TYPE_SMC,
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+ .major = 7,
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+ .minor = 1,
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+ .rev = 0,
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+ .funcs = &amdgpu_pp_ip_funcs,
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+ },
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+ {
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+ .type = AMD_IP_BLOCK_TYPE_DCE,
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+ .major = 1,
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+ .minor = 0,
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+ .rev = 0,
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+ .funcs = &dce_virtual_ip_funcs,
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+ },
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+ {
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+ .type = AMD_IP_BLOCK_TYPE_GFX,
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+ .major = 8,
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+ .minor = 0,
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+ .rev = 0,
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+ .funcs = &gfx_v8_0_ip_funcs,
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+ },
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+ {
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+ .type = AMD_IP_BLOCK_TYPE_SDMA,
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+ .major = 2,
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+ .minor = 4,
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+ .rev = 0,
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+ .funcs = &sdma_v2_4_ip_funcs,
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+ },
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+};
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+
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static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
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{
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/* ORDER MATTERS! */
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@@ -1390,8 +1444,8 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
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if (amdgpu_virtual_display) {
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switch (adev->asic_type) {
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case CHIP_TOPAZ:
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- adev->ip_blocks = topaz_ip_blocks;
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- adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
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+ adev->ip_blocks = topaz_ip_blocks_vd;
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+ adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks_vd);
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break;
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case CHIP_FIJI:
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adev->ip_blocks = fiji_ip_blocks_vd;
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