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@@ -291,6 +291,33 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
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.error_clear = SCIF_ERROR_CLEAR,
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},
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+ /*
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+ * The "SCIFA" that is in RZ/T and RZ/A2.
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+ * It looks like a normal SCIF with FIFO data, but with a
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+ * compressed address space. Also, the break out of interrupts
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+ * are different: ERI/BRI, RXI, TXI, TEI, DRI.
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+ */
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+ [SCIx_RZ_SCIFA_REGTYPE] = {
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+ .regs = {
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+ [SCSMR] = { 0x00, 16 },
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+ [SCBRR] = { 0x02, 8 },
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+ [SCSCR] = { 0x04, 16 },
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+ [SCxTDR] = { 0x06, 8 },
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+ [SCxSR] = { 0x08, 16 },
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+ [SCxRDR] = { 0x0A, 8 },
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+ [SCFCR] = { 0x0C, 16 },
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+ [SCFDR] = { 0x0E, 16 },
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+ [SCSPTR] = { 0x10, 16 },
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+ [SCLSR] = { 0x12, 16 },
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+ },
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+ .fifosize = 16,
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+ .overrun_reg = SCLSR,
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+ .overrun_mask = SCLSR_ORER,
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+ .sampling_rate_mask = SCI_SR(32),
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+ .error_mask = SCIF_DEFAULT_ERROR_MASK,
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+ .error_clear = SCIF_ERROR_CLEAR,
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+ },
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+
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/*
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* Common SH-3 SCIF definitions.
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*/
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@@ -319,15 +346,15 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
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[SCIx_SH4_SCIF_REGTYPE] = {
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.regs = {
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[SCSMR] = { 0x00, 16 },
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- [SCBRR] = { 0x02, 8 },
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- [SCSCR] = { 0x04, 16 },
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- [SCxTDR] = { 0x06, 8 },
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- [SCxSR] = { 0x08, 16 },
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- [SCxRDR] = { 0x0a, 8 },
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- [SCFCR] = { 0x0c, 16 },
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- [SCFDR] = { 0x0e, 16 },
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- [SCSPTR] = { 0x10, 16 },
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- [SCLSR] = { 0x12, 16 },
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+ [SCBRR] = { 0x04, 8 },
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+ [SCSCR] = { 0x08, 16 },
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+ [SCxTDR] = { 0x0c, 8 },
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+ [SCxSR] = { 0x10, 16 },
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+ [SCxRDR] = { 0x14, 8 },
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+ [SCFCR] = { 0x18, 16 },
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+ [SCFDR] = { 0x1c, 16 },
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+ [SCSPTR] = { 0x20, 16 },
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+ [SCLSR] = { 0x24, 16 },
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},
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.fifosize = 16,
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.overrun_reg = SCLSR,
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@@ -2810,7 +2837,7 @@ static int sci_init_single(struct platform_device *dev,
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{
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struct uart_port *port = &sci_port->port;
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const struct resource *res;
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- unsigned int i, regtype;
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+ unsigned int i;
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int ret;
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sci_port->cfg = p;
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@@ -2847,7 +2874,6 @@ static int sci_init_single(struct platform_device *dev,
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if (unlikely(sci_port->params == NULL))
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return -EINVAL;
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- regtype = sci_port->params - sci_port_params;
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switch (p->type) {
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case PORT_SCIFB:
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sci_port->rx_trigger = 48;
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@@ -2902,10 +2928,6 @@ static int sci_init_single(struct platform_device *dev,
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port->regshift = 1;
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}
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- if (regtype == SCIx_SH4_SCIF_REGTYPE)
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- if (sci_port->reg_size >= 0x20)
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- port->regshift = 1;
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-
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/*
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* The UART port needs an IRQ value, so we peg this to the RX IRQ
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* for the multi-IRQ ports, which is where we are primarily
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@@ -3110,6 +3132,10 @@ static const struct of_device_id of_sci_match[] = {
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.compatible = "renesas,scif-r7s72100",
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.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
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},
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+ {
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+ .compatible = "renesas,scif-r7s9210",
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+ .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
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+ },
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/* Family-specific types */
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{
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.compatible = "renesas,rcar-gen1-scif",
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