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+/*
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ *
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+ * Copyright (C) 2014 ARM Limited
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+ *
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+ * Author: Will Deacon <will.deacon@arm.com>
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/of_address.h>
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+#include <linux/of_pci.h>
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+#include <linux/platform_device.h>
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+
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+#include "pci-host-common.h"
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+
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+static void gen_pci_release_of_pci_ranges(struct gen_pci *pci)
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+{
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+ pci_free_resource_list(&pci->resources);
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+}
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+
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+static int gen_pci_parse_request_of_pci_ranges(struct gen_pci *pci)
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+{
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+ int err, res_valid = 0;
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+ struct device *dev = pci->host.dev.parent;
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+ struct device_node *np = dev->of_node;
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+ resource_size_t iobase;
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+ struct resource_entry *win;
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+
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+ err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources,
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+ &iobase);
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+ if (err)
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+ return err;
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+
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+ resource_list_for_each_entry(win, &pci->resources) {
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+ struct resource *parent, *res = win->res;
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+
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+ switch (resource_type(res)) {
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+ case IORESOURCE_IO:
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+ parent = &ioport_resource;
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+ err = pci_remap_iospace(res, iobase);
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+ if (err) {
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+ dev_warn(dev, "error %d: failed to map resource %pR\n",
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+ err, res);
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+ continue;
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+ }
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+ break;
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+ case IORESOURCE_MEM:
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+ parent = &iomem_resource;
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+ res_valid |= !(res->flags & IORESOURCE_PREFETCH);
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+ break;
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+ case IORESOURCE_BUS:
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+ pci->cfg.bus_range = res;
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+ default:
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+ continue;
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+ }
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+
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+ err = devm_request_resource(dev, parent, res);
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+ if (err)
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+ goto out_release_res;
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+ }
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+
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+ if (!res_valid) {
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+ dev_err(dev, "non-prefetchable memory resource required\n");
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+ err = -EINVAL;
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+ goto out_release_res;
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+ }
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+
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+ return 0;
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+
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+out_release_res:
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+ gen_pci_release_of_pci_ranges(pci);
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+ return err;
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+}
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+
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+static int gen_pci_parse_map_cfg_windows(struct gen_pci *pci)
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+{
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+ int err;
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+ u8 bus_max;
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+ resource_size_t busn;
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+ struct resource *bus_range;
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+ struct device *dev = pci->host.dev.parent;
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+ struct device_node *np = dev->of_node;
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+ u32 sz = 1 << pci->cfg.ops->bus_shift;
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+
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+ err = of_address_to_resource(np, 0, &pci->cfg.res);
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+ if (err) {
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+ dev_err(dev, "missing \"reg\" property\n");
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+ return err;
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+ }
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+
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+ /* Limit the bus-range to fit within reg */
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+ bus_max = pci->cfg.bus_range->start +
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+ (resource_size(&pci->cfg.res) >> pci->cfg.ops->bus_shift) - 1;
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+ pci->cfg.bus_range->end = min_t(resource_size_t,
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+ pci->cfg.bus_range->end, bus_max);
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+
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+ pci->cfg.win = devm_kcalloc(dev, resource_size(pci->cfg.bus_range),
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+ sizeof(*pci->cfg.win), GFP_KERNEL);
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+ if (!pci->cfg.win)
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+ return -ENOMEM;
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+
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+ /* Map our Configuration Space windows */
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+ if (!devm_request_mem_region(dev, pci->cfg.res.start,
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+ resource_size(&pci->cfg.res),
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+ "Configuration Space"))
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+ return -ENOMEM;
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+
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+ bus_range = pci->cfg.bus_range;
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+ for (busn = bus_range->start; busn <= bus_range->end; ++busn) {
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+ u32 idx = busn - bus_range->start;
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+
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+ pci->cfg.win[idx] = devm_ioremap(dev,
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+ pci->cfg.res.start + idx * sz,
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+ sz);
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+ if (!pci->cfg.win[idx])
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+ return -ENOMEM;
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+ }
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+
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+ return 0;
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+}
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+
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+int pci_host_common_probe(struct platform_device *pdev,
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+ struct gen_pci *pci)
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+{
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+ int err;
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+ const char *type;
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+ struct device *dev = &pdev->dev;
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+ struct device_node *np = dev->of_node;
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+ struct pci_bus *bus, *child;
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+
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+ type = of_get_property(np, "device_type", NULL);
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+ if (!type || strcmp(type, "pci")) {
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+ dev_err(dev, "invalid \"device_type\" %s\n", type);
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+ return -EINVAL;
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+ }
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+
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+ of_pci_check_probe_only();
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+
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+ pci->host.dev.parent = dev;
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+ INIT_LIST_HEAD(&pci->host.windows);
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+ INIT_LIST_HEAD(&pci->resources);
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+
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+ /* Parse our PCI ranges and request their resources */
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+ err = gen_pci_parse_request_of_pci_ranges(pci);
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+ if (err)
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+ return err;
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+
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+ /* Parse and map our Configuration Space windows */
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+ err = gen_pci_parse_map_cfg_windows(pci);
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+ if (err) {
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+ gen_pci_release_of_pci_ranges(pci);
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+ return err;
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+ }
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+
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+ /* Do not reassign resources if probe only */
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+ if (!pci_has_flag(PCI_PROBE_ONLY))
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+ pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
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+
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+
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+ bus = pci_scan_root_bus(dev, pci->cfg.bus_range->start,
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+ &pci->cfg.ops->ops, pci, &pci->resources);
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+ if (!bus) {
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+ dev_err(dev, "Scanning rootbus failed");
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+ return -ENODEV;
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+ }
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+
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+ pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
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+
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+ if (!pci_has_flag(PCI_PROBE_ONLY)) {
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+ pci_bus_size_bridges(bus);
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+ pci_bus_assign_resources(bus);
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+
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+ list_for_each_entry(child, &bus->children, node)
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+ pcie_bus_configure_settings(child);
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+ }
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+
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+ pci_bus_add_devices(bus);
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+ return 0;
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+}
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+
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+MODULE_DESCRIPTION("Generic PCI host driver common code");
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+MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
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+MODULE_LICENSE("GPL v2");
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David Daney