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@@ -1297,9 +1297,22 @@ static void sync_point_worker(struct work_struct *work)
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etnaviv_gpu_start_fe(gpu, addr + 2, 2);
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}
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-/*
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- * Init/Cleanup:
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- */
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+static void dump_mmu_fault(struct etnaviv_gpu *gpu)
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+{
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+ u32 status = gpu_read(gpu, VIVS_MMUv2_STATUS);
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+ int i;
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+
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+ dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
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+
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+ for (i = 0; i < 4; i++) {
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+ if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
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+ continue;
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+
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+ dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
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+ gpu_read(gpu, VIVS_MMUv2_EXCEPTION_ADDR(i)));
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+ }
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+}
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+
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static irqreturn_t irq_handler(int irq, void *data)
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{
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struct etnaviv_gpu *gpu = data;
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@@ -1320,17 +1333,7 @@ static irqreturn_t irq_handler(int irq, void *data)
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}
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if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
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- int i;
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-
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- dev_err_ratelimited(gpu->dev,
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- "MMU fault status 0x%08x\n",
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- gpu_read(gpu, VIVS_MMUv2_STATUS));
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- for (i = 0; i < 4; i++) {
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- dev_err_ratelimited(gpu->dev,
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- "MMU %d fault addr 0x%08x\n",
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- i, gpu_read(gpu,
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- VIVS_MMUv2_EXCEPTION_ADDR(i)));
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- }
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+ dump_mmu_fault(gpu);
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intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
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}
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