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@@ -1599,8 +1599,10 @@ static int tegra_sor_probe(struct platform_device *pdev)
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}
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err = tegra_output_probe(&sor->output);
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- if (err < 0)
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+ if (err < 0) {
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+ dev_err(&pdev->dev, "failed to probe output: %d\n", err);
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return err;
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+ }
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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sor->regs = devm_ioremap_resource(&pdev->dev, regs);
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@@ -1608,24 +1610,39 @@ static int tegra_sor_probe(struct platform_device *pdev)
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return PTR_ERR(sor->regs);
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sor->rst = devm_reset_control_get(&pdev->dev, "sor");
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- if (IS_ERR(sor->rst))
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+ if (IS_ERR(sor->rst)) {
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+ dev_err(&pdev->dev, "failed to get reset control: %ld\n",
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+ PTR_ERR(sor->rst));
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return PTR_ERR(sor->rst);
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+ }
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sor->clk = devm_clk_get(&pdev->dev, NULL);
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- if (IS_ERR(sor->clk))
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+ if (IS_ERR(sor->clk)) {
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+ dev_err(&pdev->dev, "failed to get module clock: %ld\n",
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+ PTR_ERR(sor->clk));
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return PTR_ERR(sor->clk);
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+ }
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sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
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- if (IS_ERR(sor->clk_parent))
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+ if (IS_ERR(sor->clk_parent)) {
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+ dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
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+ PTR_ERR(sor->clk_parent));
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return PTR_ERR(sor->clk_parent);
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+ }
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sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
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- if (IS_ERR(sor->clk_safe))
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+ if (IS_ERR(sor->clk_safe)) {
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+ dev_err(&pdev->dev, "failed to get safe clock: %ld\n",
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+ PTR_ERR(sor->clk_safe));
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return PTR_ERR(sor->clk_safe);
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+ }
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sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
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- if (IS_ERR(sor->clk_dp))
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+ if (IS_ERR(sor->clk_dp)) {
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+ dev_err(&pdev->dev, "failed to get DP clock: %ld\n",
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+ PTR_ERR(sor->clk_dp));
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return PTR_ERR(sor->clk_dp);
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+ }
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INIT_LIST_HEAD(&sor->client.list);
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sor->client.ops = &sor_client_ops;
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