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@@ -115,7 +115,9 @@ static int mtu3_device_enable(struct mtu3 *mtu)
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mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
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mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
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(SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
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(SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
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SSUSB_U2_PORT_HOST_SEL));
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SSUSB_U2_PORT_HOST_SEL));
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- mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
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+
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+ if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
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+ mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
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return ssusb_check_clocks(mtu->ssusb, check_clk);
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return ssusb_check_clocks(mtu->ssusb, check_clk);
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}
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}
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@@ -130,7 +132,10 @@ static void mtu3_device_disable(struct mtu3 *mtu)
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mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
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mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
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SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
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SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
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- mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
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+
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+ if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
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+ mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
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+
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mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
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mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
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}
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}
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