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@@ -3488,9 +3488,9 @@ gen4_signal_levels(uint8_t train_set)
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return signal_levels;
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}
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-/* Gen6's DP voltage swing and pre-emphasis control */
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+/* SNB CPU eDP voltage swing and pre-emphasis control */
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static uint32_t
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-gen6_edp_signal_levels(uint8_t train_set)
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+snb_cpu_edp_signal_levels(uint8_t train_set)
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{
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int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
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DP_TRAIN_PRE_EMPHASIS_MASK);
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@@ -3516,9 +3516,9 @@ gen6_edp_signal_levels(uint8_t train_set)
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}
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}
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-/* Gen7's DP voltage swing and pre-emphasis control */
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+/* IVB CPU eDP voltage swing and pre-emphasis control */
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static uint32_t
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-gen7_edp_signal_levels(uint8_t train_set)
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+ivb_cpu_edp_signal_levels(uint8_t train_set)
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{
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int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
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DP_TRAIN_PRE_EMPHASIS_MASK);
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@@ -3566,10 +3566,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
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} else if (IS_VALLEYVIEW(dev_priv)) {
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signal_levels = vlv_signal_levels(intel_dp);
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} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
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- signal_levels = gen7_edp_signal_levels(train_set);
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+ signal_levels = ivb_cpu_edp_signal_levels(train_set);
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mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
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} else if (IS_GEN6(dev_priv) && port == PORT_A) {
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- signal_levels = gen6_edp_signal_levels(train_set);
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+ signal_levels = snb_cpu_edp_signal_levels(train_set);
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mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
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} else {
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signal_levels = gen4_signal_levels(train_set);
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