|
@@ -12,6 +12,10 @@ bool pkey_execute_disable_supported;
|
|
|
int pkeys_total; /* Total pkeys as per device tree */
|
|
|
u32 initial_allocation_mask; /* Bits set for reserved keys */
|
|
|
|
|
|
+#define AMR_BITS_PER_PKEY 2
|
|
|
+#define PKEY_REG_BITS (sizeof(u64)*8)
|
|
|
+#define pkeyshift(pkey) (PKEY_REG_BITS - ((pkey+1) * AMR_BITS_PER_PKEY))
|
|
|
+
|
|
|
int pkey_initialize(void)
|
|
|
{
|
|
|
int os_reserved, i;
|
|
@@ -103,3 +107,46 @@ static inline void write_uamor(u64 value)
|
|
|
{
|
|
|
mtspr(SPRN_UAMOR, value);
|
|
|
}
|
|
|
+
|
|
|
+static inline void init_amr(int pkey, u8 init_bits)
|
|
|
+{
|
|
|
+ u64 new_amr_bits = (((u64)init_bits & 0x3UL) << pkeyshift(pkey));
|
|
|
+ u64 old_amr = read_amr() & ~((u64)(0x3ul) << pkeyshift(pkey));
|
|
|
+
|
|
|
+ write_amr(old_amr | new_amr_bits);
|
|
|
+}
|
|
|
+
|
|
|
+static inline void init_iamr(int pkey, u8 init_bits)
|
|
|
+{
|
|
|
+ u64 new_iamr_bits = (((u64)init_bits & 0x1UL) << pkeyshift(pkey));
|
|
|
+ u64 old_iamr = read_iamr() & ~((u64)(0x1ul) << pkeyshift(pkey));
|
|
|
+
|
|
|
+ write_iamr(old_iamr | new_iamr_bits);
|
|
|
+}
|
|
|
+
|
|
|
+static void pkey_status_change(int pkey, bool enable)
|
|
|
+{
|
|
|
+ u64 old_uamor;
|
|
|
+
|
|
|
+ /* Reset the AMR and IAMR bits for this key */
|
|
|
+ init_amr(pkey, 0x0);
|
|
|
+ init_iamr(pkey, 0x0);
|
|
|
+
|
|
|
+ /* Enable/disable key */
|
|
|
+ old_uamor = read_uamor();
|
|
|
+ if (enable)
|
|
|
+ old_uamor |= (0x3ul << pkeyshift(pkey));
|
|
|
+ else
|
|
|
+ old_uamor &= ~(0x3ul << pkeyshift(pkey));
|
|
|
+ write_uamor(old_uamor);
|
|
|
+}
|
|
|
+
|
|
|
+void __arch_activate_pkey(int pkey)
|
|
|
+{
|
|
|
+ pkey_status_change(pkey, true);
|
|
|
+}
|
|
|
+
|
|
|
+void __arch_deactivate_pkey(int pkey)
|
|
|
+{
|
|
|
+ pkey_status_change(pkey, false);
|
|
|
+}
|