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@@ -368,29 +368,29 @@ enum vmcs_field {
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#define TYPE_PHYSICAL_APIC_EVENT (10 << 12)
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#define TYPE_PHYSICAL_APIC_INST (15 << 12)
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-/* segment AR */
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-#define SEGMENT_AR_L_MASK (1 << 13)
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-
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-#define AR_TYPE_ACCESSES_MASK 1
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-#define AR_TYPE_READABLE_MASK (1 << 1)
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-#define AR_TYPE_WRITEABLE_MASK (1 << 2)
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-#define AR_TYPE_CODE_MASK (1 << 3)
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-#define AR_TYPE_MASK 0x0f
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-#define AR_TYPE_BUSY_64_TSS 11
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-#define AR_TYPE_BUSY_32_TSS 11
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-#define AR_TYPE_BUSY_16_TSS 3
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-#define AR_TYPE_LDT 2
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-
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-#define AR_UNUSABLE_MASK (1 << 16)
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-#define AR_S_MASK (1 << 4)
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-#define AR_P_MASK (1 << 7)
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-#define AR_L_MASK (1 << 13)
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-#define AR_DB_MASK (1 << 14)
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-#define AR_G_MASK (1 << 15)
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-#define AR_DPL_SHIFT 5
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-#define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
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-
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-#define AR_RESERVD_MASK 0xfffe0f00
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+/* segment AR in VMCS -- these are different from what LAR reports */
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+#define VMX_SEGMENT_AR_L_MASK (1 << 13)
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+
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+#define VMX_AR_TYPE_ACCESSES_MASK 1
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+#define VMX_AR_TYPE_READABLE_MASK (1 << 1)
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+#define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
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+#define VMX_AR_TYPE_CODE_MASK (1 << 3)
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+#define VMX_AR_TYPE_MASK 0x0f
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+#define VMX_AR_TYPE_BUSY_64_TSS 11
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+#define VMX_AR_TYPE_BUSY_32_TSS 11
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+#define VMX_AR_TYPE_BUSY_16_TSS 3
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+#define VMX_AR_TYPE_LDT 2
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+
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+#define VMX_AR_UNUSABLE_MASK (1 << 16)
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+#define VMX_AR_S_MASK (1 << 4)
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+#define VMX_AR_P_MASK (1 << 7)
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+#define VMX_AR_L_MASK (1 << 13)
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+#define VMX_AR_DB_MASK (1 << 14)
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+#define VMX_AR_G_MASK (1 << 15)
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+#define VMX_AR_DPL_SHIFT 5
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+#define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3)
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+
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+#define VMX_AR_RESERVD_MASK 0xfffe0f00
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#define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
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#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1)
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