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@@ -1500,6 +1500,8 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
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u32 hprt0;
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u32 pcgctl;
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+ spin_lock_irqsave(&hsotg->lock, flags);
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+
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/*
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* If hibernation is supported, Phy clock is already resumed
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* after registers restore.
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@@ -1508,10 +1510,11 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
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pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
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pcgctl &= ~PCGCTL_STOPPCLK;
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dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
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+ spin_unlock_irqrestore(&hsotg->lock, flags);
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usleep_range(20000, 40000);
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+ spin_lock_irqsave(&hsotg->lock, flags);
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}
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- spin_lock_irqsave(&hsotg->lock, flags);
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hprt0 = dwc2_read_hprt0(hsotg);
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hprt0 |= HPRT0_RES;
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hprt0 &= ~HPRT0_SUSP;
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