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@@ -479,6 +479,11 @@ static const struct amdgpu_ip_block_version vega10_common_ip_block =
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.funcs = &soc15_common_ip_funcs,
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};
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+static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
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+{
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+ return adev->nbio_funcs->get_rev_id(adev);
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+}
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+
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int soc15_set_ip_blocks(struct amdgpu_device *adev)
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{
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/* Set IP register base before any HW register access */
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@@ -507,6 +512,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
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adev->df_funcs = &df_v3_6_funcs;
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else
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adev->df_funcs = &df_v1_7_funcs;
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+
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+ adev->rev_id = soc15_get_rev_id(adev);
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adev->nbio_funcs->detect_hw_virt(adev);
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if (amdgpu_sriov_vf(adev))
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@@ -581,11 +588,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
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return 0;
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}
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-static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
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-{
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- return adev->nbio_funcs->get_rev_id(adev);
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-}
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-
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static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
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{
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adev->nbio_funcs->hdp_flush(adev, ring);
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@@ -642,7 +644,6 @@ static int soc15_common_early_init(void *handle)
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adev->asic_funcs = &soc15_asic_funcs;
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- adev->rev_id = soc15_get_rev_id(adev);
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adev->external_rev_id = 0xFF;
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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