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@@ -214,32 +214,6 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
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pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
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}
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-int
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-pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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-{
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- struct mt7621_pcie *pcie = dev->bus->sysdata;
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- u16 cmd;
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- u32 val;
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- int irq;
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-
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- if (dev->bus->number == 0) {
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- write_config(pcie, slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
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- val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
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- printk("BAR0 at slot %d = %x\n", slot, val);
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- }
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-
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- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
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- pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
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- pci_read_config_word(dev, PCI_COMMAND, &cmd);
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- cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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- pci_write_config_word(dev, PCI_COMMAND, cmd);
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-
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- irq = of_irq_parse_and_map_pci(dev, slot, pin);
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-
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- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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- return irq;
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-}
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-
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void
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set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
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int start_b, int bits, int val)
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@@ -461,7 +435,7 @@ static int mt7621_pcie_register_host(struct pci_host_bridge *host,
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host->busnr = pcie->busn.start;
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host->dev.parent = pcie->dev;
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host->ops = &mt7621_pci_ops;
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- host->map_irq = pcibios_map_irq;
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+ host->map_irq = of_irq_parse_and_map_pci;
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host->swizzle_irq = pci_common_swizzle;
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host->sysdata = pcie;
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@@ -726,11 +700,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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return 0;
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}
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-int pcibios_plat_dev_init(struct pci_dev *dev)
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-{
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- return 0;
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-}
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-
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static const struct of_device_id mt7621_pci_ids[] = {
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{ .compatible = "mediatek,mt7621-pci" },
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{},
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