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@@ -51,8 +51,11 @@ static int mv88e6171_switch_reset(struct dsa_switch *ds)
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/* Wait for transmit queues to drain. */
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usleep_range(2000, 4000);
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- /* Reset the switch. */
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- REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
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+ /* Reset the switch. Keep PPU active. The PPU needs to be
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+ * active to support indirect phy register accesses through
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+ * global registers 0x18 and 0x19.
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+ */
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+ REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
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/* Wait up to one second for reset to complete. */
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timeout = jiffies + 1 * HZ;
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@@ -83,11 +86,10 @@ static int mv88e6171_setup_global(struct dsa_switch *ds)
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int ret;
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int i;
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- /* Disable the PHY polling unit (since there won't be any
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- * external PHYs to poll), don't discard packets with
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- * excessive collisions, and mask all interrupt sources.
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+ /* Discard packets with excessive collisions, mask all
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+ * interrupt sources, enable PPU.
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*/
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- REG_WRITE(REG_GLOBAL, 0x04, 0x0000);
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+ REG_WRITE(REG_GLOBAL, 0x04, 0x6000);
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/* Set the default address aging time to 5 minutes, and
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* enable address learn messages to be sent to all message
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@@ -336,7 +338,7 @@ mv88e6171_phy_read(struct dsa_switch *ds, int port, int regnum)
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int ret;
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mutex_lock(&ps->phy_mutex);
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- ret = mv88e6xxx_phy_read(ds, addr, regnum);
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+ ret = mv88e6xxx_phy_read_indirect(ds, addr, regnum);
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mutex_unlock(&ps->phy_mutex);
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return ret;
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}
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@@ -350,7 +352,7 @@ mv88e6171_phy_write(struct dsa_switch *ds,
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int ret;
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mutex_lock(&ps->phy_mutex);
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- ret = mv88e6xxx_phy_write(ds, addr, regnum, val);
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+ ret = mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
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mutex_unlock(&ps->phy_mutex);
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return ret;
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}
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