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drm/amd/powerplay: enable voltage control by default for dgpu.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu vor 8 Jahren
Ursprung
Commit
4c696ecf4f
1 geänderte Dateien mit 3 neuen und 6 gelöschten Zeilen
  1. 3 6
      drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

+ 3 - 6
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

@@ -80,20 +80,17 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
 		switch (hwmgr->chip_id) {
 		switch (hwmgr->chip_id) {
 		case CHIP_TOPAZ:
 		case CHIP_TOPAZ:
 			topaz_set_asic_special_caps(hwmgr);
 			topaz_set_asic_special_caps(hwmgr);
-			hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK |
-						PP_VBI_TIME_SUPPORT_MASK |
+			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
 						PP_ENABLE_GFX_CG_THRU_SMU);
 						PP_ENABLE_GFX_CG_THRU_SMU);
 			hwmgr->pp_table_version = PP_TABLE_V0;
 			hwmgr->pp_table_version = PP_TABLE_V0;
 			break;
 			break;
 		case CHIP_TONGA:
 		case CHIP_TONGA:
 			tonga_set_asic_special_caps(hwmgr);
 			tonga_set_asic_special_caps(hwmgr);
-			hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK |
-						PP_VBI_TIME_SUPPORT_MASK);
+			hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
 			break;
 			break;
 		case CHIP_FIJI:
 		case CHIP_FIJI:
 			fiji_set_asic_special_caps(hwmgr);
 			fiji_set_asic_special_caps(hwmgr);
-			hwmgr->feature_mask &= ~(PP_SMC_VOLTAGE_CONTROL_MASK |
-						PP_VBI_TIME_SUPPORT_MASK |
+			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
 						PP_ENABLE_GFX_CG_THRU_SMU);
 						PP_ENABLE_GFX_CG_THRU_SMU);
 			break;
 			break;
 		case CHIP_POLARIS11:
 		case CHIP_POLARIS11: