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@@ -383,6 +383,12 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
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ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
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ib_size_alignment = 1;
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ib_size_alignment = 1;
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break;
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break;
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+ case AMDGPU_HW_IP_VCN_JPEG:
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+ type = AMD_IP_BLOCK_TYPE_VCN;
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+ ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0;
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+ ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
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+ ib_size_alignment = 16;
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+ break;
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default:
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default:
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return -EINVAL;
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return -EINVAL;
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}
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}
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@@ -427,6 +433,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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break;
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break;
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case AMDGPU_HW_IP_VCN_DEC:
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case AMDGPU_HW_IP_VCN_DEC:
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case AMDGPU_HW_IP_VCN_ENC:
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case AMDGPU_HW_IP_VCN_ENC:
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+ case AMDGPU_HW_IP_VCN_JPEG:
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type = AMD_IP_BLOCK_TYPE_VCN;
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type = AMD_IP_BLOCK_TYPE_VCN;
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break;
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break;
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default:
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default:
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