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@@ -16,6 +16,33 @@
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*
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*/
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+/*
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+ * The MMCIF driver is now processing MMC requests asynchronously, according
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+ * to the Linux MMC API requirement.
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+ *
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+ * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
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+ * data, and optional stop. To achieve asynchronous processing each of these
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+ * stages is split into two halves: a top and a bottom half. The top half
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+ * initialises the hardware, installs a timeout handler to handle completion
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+ * timeouts, and returns. In case of the command stage this immediately returns
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+ * control to the caller, leaving all further processing to run asynchronously.
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+ * All further request processing is performed by the bottom halves.
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+ *
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+ * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
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+ * thread, a DMA completion callback, if DMA is used, a timeout work, and
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+ * request- and stage-specific handler methods.
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+ *
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+ * Each bottom half run begins with either a hardware interrupt, a DMA callback
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+ * invocation, or a timeout work run. In case of an error or a successful
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+ * processing completion, the MMC core is informed and the request processing is
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+ * finished. In case processing has to continue, i.e., if data has to be read
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+ * from or written to the card, or if a stop command has to be sent, the next
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+ * top half is called, which performs the necessary hardware handling and
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+ * reschedules the timeout work. This returns the driver state machine into the
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+ * bottom half waiting state.
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+ */
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+
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+#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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@@ -123,6 +150,11 @@
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#define MASK_MRBSYTO (1 << 1)
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#define MASK_MRSPTO (1 << 0)
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+#define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
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+ MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
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+ MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
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+ MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
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+
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/* CE_HOST_STS1 */
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#define STS1_CMDSEQ (1 << 31)
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@@ -162,9 +194,21 @@ enum mmcif_state {
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STATE_IOS,
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};
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+enum mmcif_wait_for {
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+ MMCIF_WAIT_FOR_REQUEST,
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+ MMCIF_WAIT_FOR_CMD,
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+ MMCIF_WAIT_FOR_MREAD,
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+ MMCIF_WAIT_FOR_MWRITE,
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+ MMCIF_WAIT_FOR_READ,
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+ MMCIF_WAIT_FOR_WRITE,
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+ MMCIF_WAIT_FOR_READ_END,
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+ MMCIF_WAIT_FOR_WRITE_END,
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+ MMCIF_WAIT_FOR_STOP,
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+};
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+
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struct sh_mmcif_host {
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struct mmc_host *mmc;
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- struct mmc_data *data;
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+ struct mmc_request *mrq;
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struct platform_device *pd;
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struct sh_dmae_slave dma_slave_tx;
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struct sh_dmae_slave dma_slave_rx;
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@@ -172,11 +216,17 @@ struct sh_mmcif_host {
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unsigned int clk;
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int bus_width;
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bool sd_error;
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+ bool dying;
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long timeout;
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void __iomem *addr;
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- struct completion intr_wait;
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+ u32 *pio_ptr;
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+ spinlock_t lock; /* protect sh_mmcif_host::state */
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enum mmcif_state state;
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- spinlock_t lock;
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+ enum mmcif_wait_for wait_for;
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+ struct delayed_work timeout_work;
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+ size_t blocksize;
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+ int sg_idx;
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+ int sg_blkidx;
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bool power;
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bool card_present;
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@@ -202,19 +252,21 @@ static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
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static void mmcif_dma_complete(void *arg)
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{
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struct sh_mmcif_host *host = arg;
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+ struct mmc_data *data = host->mrq->data;
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+
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dev_dbg(&host->pd->dev, "Command completed\n");
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- if (WARN(!host->data, "%s: NULL data in DMA completion!\n",
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+ if (WARN(!data, "%s: NULL data in DMA completion!\n",
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dev_name(&host->pd->dev)))
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return;
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- if (host->data->flags & MMC_DATA_READ)
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+ if (data->flags & MMC_DATA_READ)
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dma_unmap_sg(host->chan_rx->device->dev,
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- host->data->sg, host->data->sg_len,
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+ data->sg, data->sg_len,
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DMA_FROM_DEVICE);
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else
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dma_unmap_sg(host->chan_tx->device->dev,
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- host->data->sg, host->data->sg_len,
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+ data->sg, data->sg_len,
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DMA_TO_DEVICE);
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complete(&host->dma_complete);
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@@ -222,13 +274,14 @@ static void mmcif_dma_complete(void *arg)
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static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
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{
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- struct scatterlist *sg = host->data->sg;
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+ struct mmc_data *data = host->mrq->data;
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+ struct scatterlist *sg = data->sg;
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struct dma_async_tx_descriptor *desc = NULL;
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struct dma_chan *chan = host->chan_rx;
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dma_cookie_t cookie = -EINVAL;
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int ret;
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- ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
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+ ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
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DMA_FROM_DEVICE);
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if (ret > 0) {
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host->dma_active = true;
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@@ -244,7 +297,7 @@ static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
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dma_async_issue_pending(chan);
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}
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dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
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- __func__, host->data->sg_len, ret, cookie);
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+ __func__, data->sg_len, ret, cookie);
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if (!desc) {
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/* DMA failed, fall back to PIO */
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@@ -265,18 +318,19 @@ static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
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}
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dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
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- desc, cookie, host->data->sg_len);
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+ desc, cookie, data->sg_len);
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}
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static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
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{
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- struct scatterlist *sg = host->data->sg;
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+ struct mmc_data *data = host->mrq->data;
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+ struct scatterlist *sg = data->sg;
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struct dma_async_tx_descriptor *desc = NULL;
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struct dma_chan *chan = host->chan_tx;
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dma_cookie_t cookie = -EINVAL;
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int ret;
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- ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
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+ ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
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DMA_TO_DEVICE);
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if (ret > 0) {
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host->dma_active = true;
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@@ -292,7 +346,7 @@ static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
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dma_async_issue_pending(chan);
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}
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dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
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- __func__, host->data->sg_len, ret, cookie);
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+ __func__, data->sg_len, ret, cookie);
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if (!desc) {
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/* DMA failed, fall back to PIO */
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@@ -399,7 +453,7 @@ static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
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sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
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else
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sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
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- (ilog2(__rounddown_pow_of_two(host->clk / clk)) << 16));
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+ ((fls(host->clk / clk) - 1) << 16));
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sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
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}
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@@ -421,7 +475,7 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
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static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
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{
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u32 state1, state2;
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- int ret, timeout = 10000000;
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+ int ret, timeout;
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host->sd_error = false;
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@@ -433,155 +487,212 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
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if (state1 & STS1_CMDSEQ) {
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sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
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sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
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- while (1) {
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- timeout--;
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- if (timeout < 0) {
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- dev_err(&host->pd->dev,
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- "Forceed end of command sequence timeout err\n");
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- return -EIO;
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- }
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+ for (timeout = 10000000; timeout; timeout--) {
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if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
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- & STS1_CMDSEQ))
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+ & STS1_CMDSEQ))
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break;
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mdelay(1);
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}
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+ if (!timeout) {
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+ dev_err(&host->pd->dev,
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+ "Forced end of command sequence timeout err\n");
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+ return -EIO;
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+ }
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sh_mmcif_sync_reset(host);
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dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
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return -EIO;
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}
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if (state2 & STS2_CRC_ERR) {
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- dev_dbg(&host->pd->dev, ": Happened CRC error\n");
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+ dev_dbg(&host->pd->dev, ": CRC error\n");
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ret = -EIO;
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} else if (state2 & STS2_TIMEOUT_ERR) {
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- dev_dbg(&host->pd->dev, ": Happened Timeout error\n");
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+ dev_dbg(&host->pd->dev, ": Timeout\n");
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ret = -ETIMEDOUT;
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} else {
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- dev_dbg(&host->pd->dev, ": Happened End/Index error\n");
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+ dev_dbg(&host->pd->dev, ": End/Index error\n");
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ret = -EIO;
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}
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return ret;
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}
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-static int sh_mmcif_single_read(struct sh_mmcif_host *host,
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- struct mmc_request *mrq)
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+static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
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{
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- struct mmc_data *data = mrq->data;
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- long time;
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- u32 blocksize, i, *p = sg_virt(data->sg);
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+ struct mmc_data *data = host->mrq->data;
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+
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+ host->sg_blkidx += host->blocksize;
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+
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+ /* data->sg->length must be a multiple of host->blocksize? */
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+ BUG_ON(host->sg_blkidx > data->sg->length);
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+
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+ if (host->sg_blkidx == data->sg->length) {
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+ host->sg_blkidx = 0;
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+ if (++host->sg_idx < data->sg_len)
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+ host->pio_ptr = sg_virt(++data->sg);
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+ } else {
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+ host->pio_ptr = p;
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+ }
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+
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+ if (host->sg_idx == data->sg_len)
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+ return false;
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+
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+ return true;
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+}
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+
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+static void sh_mmcif_single_read(struct sh_mmcif_host *host,
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+ struct mmc_request *mrq)
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+{
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+ host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
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+ BLOCK_SIZE_MASK) + 3;
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+
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+ host->wait_for = MMCIF_WAIT_FOR_READ;
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+ schedule_delayed_work(&host->timeout_work, host->timeout);
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/* buf read enable */
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
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- time = wait_for_completion_interruptible_timeout(&host->intr_wait,
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- host->timeout);
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- if (time <= 0 || host->sd_error)
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- return sh_mmcif_error_manage(host);
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-
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- blocksize = (BLOCK_SIZE_MASK &
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- sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
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- for (i = 0; i < blocksize / 4; i++)
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+}
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+
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+static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
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+{
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+ struct mmc_data *data = host->mrq->data;
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+ u32 *p = sg_virt(data->sg);
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+ int i;
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+
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+ if (host->sd_error) {
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+ data->error = sh_mmcif_error_manage(host);
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+ return false;
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+ }
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+
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+ for (i = 0; i < host->blocksize / 4; i++)
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*p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
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/* buffer read end */
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sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
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- time = wait_for_completion_interruptible_timeout(&host->intr_wait,
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- host->timeout);
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- if (time <= 0 || host->sd_error)
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- return sh_mmcif_error_manage(host);
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+ host->wait_for = MMCIF_WAIT_FOR_READ_END;
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- return 0;
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+ return true;
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}
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-static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
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- struct mmc_request *mrq)
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+static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
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+ struct mmc_request *mrq)
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{
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struct mmc_data *data = mrq->data;
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- long time;
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- u32 blocksize, i, j, sec, *p;
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-
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- blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
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- MMCIF_CE_BLOCK_SET);
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- for (j = 0; j < data->sg_len; j++) {
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- p = sg_virt(data->sg);
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- for (sec = 0; sec < data->sg->length / blocksize; sec++) {
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- sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
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- /* buf read enable */
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- time = wait_for_completion_interruptible_timeout(&host->intr_wait,
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- host->timeout);
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-
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- if (time <= 0 || host->sd_error)
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- return sh_mmcif_error_manage(host);
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-
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- for (i = 0; i < blocksize / 4; i++)
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- *p++ = sh_mmcif_readl(host->addr,
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- MMCIF_CE_DATA);
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- }
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- if (j < data->sg_len - 1)
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- data->sg++;
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+
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+ if (!data->sg_len || !data->sg->length)
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+ return;
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+
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+ host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
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+ BLOCK_SIZE_MASK;
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+
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+ host->wait_for = MMCIF_WAIT_FOR_MREAD;
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+ host->sg_idx = 0;
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+ host->sg_blkidx = 0;
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+ host->pio_ptr = sg_virt(data->sg);
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+ schedule_delayed_work(&host->timeout_work, host->timeout);
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+ sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
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+}
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+
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+static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
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+{
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+ struct mmc_data *data = host->mrq->data;
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+ u32 *p = host->pio_ptr;
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+ int i;
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+
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+ if (host->sd_error) {
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+ data->error = sh_mmcif_error_manage(host);
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+ return false;
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}
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- return 0;
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+
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+ BUG_ON(!data->sg->length);
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+
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+ for (i = 0; i < host->blocksize / 4; i++)
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+ *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
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+
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+ if (!sh_mmcif_next_block(host, p))
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+ return false;
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+
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+ schedule_delayed_work(&host->timeout_work, host->timeout);
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+ sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
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+
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+ return true;
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}
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-static int sh_mmcif_single_write(struct sh_mmcif_host *host,
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+static void sh_mmcif_single_write(struct sh_mmcif_host *host,
|
|
|
struct mmc_request *mrq)
|
|
|
{
|
|
|
- struct mmc_data *data = mrq->data;
|
|
|
- long time;
|
|
|
- u32 blocksize, i, *p = sg_virt(data->sg);
|
|
|
+ host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
|
|
|
+ BLOCK_SIZE_MASK) + 3;
|
|
|
|
|
|
- sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
|
|
|
+ host->wait_for = MMCIF_WAIT_FOR_WRITE;
|
|
|
+ schedule_delayed_work(&host->timeout_work, host->timeout);
|
|
|
|
|
|
/* buf write enable */
|
|
|
- time = wait_for_completion_interruptible_timeout(&host->intr_wait,
|
|
|
- host->timeout);
|
|
|
- if (time <= 0 || host->sd_error)
|
|
|
- return sh_mmcif_error_manage(host);
|
|
|
-
|
|
|
- blocksize = (BLOCK_SIZE_MASK &
|
|
|
- sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
|
|
|
- for (i = 0; i < blocksize / 4; i++)
|
|
|
+ sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
|
|
|
+}
|
|
|
+
|
|
|
+static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
|
|
|
+{
|
|
|
+ struct mmc_data *data = host->mrq->data;
|
|
|
+ u32 *p = sg_virt(data->sg);
|
|
|
+ int i;
|
|
|
+
|
|
|
+ if (host->sd_error) {
|
|
|
+ data->error = sh_mmcif_error_manage(host);
|
|
|
+ return false;
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = 0; i < host->blocksize / 4; i++)
|
|
|
sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
|
|
|
|
|
|
/* buffer write end */
|
|
|
sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
|
|
|
+ host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
|
|
|
|
|
|
- time = wait_for_completion_interruptible_timeout(&host->intr_wait,
|
|
|
- host->timeout);
|
|
|
- if (time <= 0 || host->sd_error)
|
|
|
- return sh_mmcif_error_manage(host);
|
|
|
-
|
|
|
- return 0;
|
|
|
+ return true;
|
|
|
}
|
|
|
|
|
|
-static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
|
|
|
- struct mmc_request *mrq)
|
|
|
+static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
|
|
|
+ struct mmc_request *mrq)
|
|
|
{
|
|
|
struct mmc_data *data = mrq->data;
|
|
|
- long time;
|
|
|
- u32 i, sec, j, blocksize, *p;
|
|
|
|
|
|
- blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
|
|
|
- MMCIF_CE_BLOCK_SET);
|
|
|
+ if (!data->sg_len || !data->sg->length)
|
|
|
+ return;
|
|
|
|
|
|
- for (j = 0; j < data->sg_len; j++) {
|
|
|
- p = sg_virt(data->sg);
|
|
|
- for (sec = 0; sec < data->sg->length / blocksize; sec++) {
|
|
|
- sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
|
|
|
- /* buf write enable*/
|
|
|
- time = wait_for_completion_interruptible_timeout(&host->intr_wait,
|
|
|
- host->timeout);
|
|
|
+ host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
|
|
|
+ BLOCK_SIZE_MASK;
|
|
|
|
|
|
- if (time <= 0 || host->sd_error)
|
|
|
- return sh_mmcif_error_manage(host);
|
|
|
+ host->wait_for = MMCIF_WAIT_FOR_MWRITE;
|
|
|
+ host->sg_idx = 0;
|
|
|
+ host->sg_blkidx = 0;
|
|
|
+ host->pio_ptr = sg_virt(data->sg);
|
|
|
+ schedule_delayed_work(&host->timeout_work, host->timeout);
|
|
|
+ sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
|
|
|
+}
|
|
|
|
|
|
- for (i = 0; i < blocksize / 4; i++)
|
|
|
- sh_mmcif_writel(host->addr,
|
|
|
- MMCIF_CE_DATA, *p++);
|
|
|
- }
|
|
|
- if (j < data->sg_len - 1)
|
|
|
- data->sg++;
|
|
|
+static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
|
|
|
+{
|
|
|
+ struct mmc_data *data = host->mrq->data;
|
|
|
+ u32 *p = host->pio_ptr;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ if (host->sd_error) {
|
|
|
+ data->error = sh_mmcif_error_manage(host);
|
|
|
+ return false;
|
|
|
}
|
|
|
- return 0;
|
|
|
+
|
|
|
+ BUG_ON(!data->sg->length);
|
|
|
+
|
|
|
+ for (i = 0; i < host->blocksize / 4; i++)
|
|
|
+ sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
|
|
|
+
|
|
|
+ if (!sh_mmcif_next_block(host, p))
|
|
|
+ return false;
|
|
|
+
|
|
|
+ schedule_delayed_work(&host->timeout_work, host->timeout);
|
|
|
+ sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
|
|
|
+
|
|
|
+ return true;
|
|
|
}
|
|
|
|
|
|
static void sh_mmcif_get_response(struct sh_mmcif_host *host,
|
|
@@ -603,8 +714,11 @@ static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
|
|
|
}
|
|
|
|
|
|
static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
|
|
|
- struct mmc_request *mrq, struct mmc_command *cmd, u32 opc)
|
|
|
+ struct mmc_request *mrq)
|
|
|
{
|
|
|
+ struct mmc_data *data = mrq->data;
|
|
|
+ struct mmc_command *cmd = mrq->cmd;
|
|
|
+ u32 opc = cmd->opcode;
|
|
|
u32 tmp = 0;
|
|
|
|
|
|
/* Response Type check */
|
|
@@ -636,7 +750,7 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
|
|
|
break;
|
|
|
}
|
|
|
/* WDAT / DATW */
|
|
|
- if (host->data) {
|
|
|
+ if (data) {
|
|
|
tmp |= CMD_SET_WDAT;
|
|
|
switch (host->bus_width) {
|
|
|
case MMC_BUS_WIDTH_1:
|
|
@@ -660,7 +774,7 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
|
|
|
if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
|
|
|
tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
|
|
|
sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
|
|
|
- mrq->data->blocks << 16);
|
|
|
+ data->blocks << 16);
|
|
|
}
|
|
|
/* RIDXC[1:0] check bits */
|
|
|
if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
|
|
@@ -674,68 +788,60 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
|
|
|
opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
|
|
|
tmp |= CMD_SET_CRC7C_INTERNAL;
|
|
|
|
|
|
- return opc = ((opc << 24) | tmp);
|
|
|
+ return (opc << 24) | tmp;
|
|
|
}
|
|
|
|
|
|
static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
|
|
|
- struct mmc_request *mrq, u32 opc)
|
|
|
+ struct mmc_request *mrq, u32 opc)
|
|
|
{
|
|
|
- int ret;
|
|
|
-
|
|
|
switch (opc) {
|
|
|
case MMC_READ_MULTIPLE_BLOCK:
|
|
|
- ret = sh_mmcif_multi_read(host, mrq);
|
|
|
- break;
|
|
|
+ sh_mmcif_multi_read(host, mrq);
|
|
|
+ return 0;
|
|
|
case MMC_WRITE_MULTIPLE_BLOCK:
|
|
|
- ret = sh_mmcif_multi_write(host, mrq);
|
|
|
- break;
|
|
|
+ sh_mmcif_multi_write(host, mrq);
|
|
|
+ return 0;
|
|
|
case MMC_WRITE_BLOCK:
|
|
|
- ret = sh_mmcif_single_write(host, mrq);
|
|
|
- break;
|
|
|
+ sh_mmcif_single_write(host, mrq);
|
|
|
+ return 0;
|
|
|
case MMC_READ_SINGLE_BLOCK:
|
|
|
case MMC_SEND_EXT_CSD:
|
|
|
- ret = sh_mmcif_single_read(host, mrq);
|
|
|
- break;
|
|
|
+ sh_mmcif_single_read(host, mrq);
|
|
|
+ return 0;
|
|
|
default:
|
|
|
dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
|
|
|
- ret = -EINVAL;
|
|
|
- break;
|
|
|
+ return -EINVAL;
|
|
|
}
|
|
|
- return ret;
|
|
|
}
|
|
|
|
|
|
static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
|
|
|
- struct mmc_request *mrq, struct mmc_command *cmd)
|
|
|
+ struct mmc_request *mrq)
|
|
|
{
|
|
|
- long time;
|
|
|
- int ret = 0, mask = 0;
|
|
|
+ struct mmc_command *cmd = mrq->cmd;
|
|
|
u32 opc = cmd->opcode;
|
|
|
+ u32 mask;
|
|
|
|
|
|
switch (opc) {
|
|
|
- /* respons busy check */
|
|
|
+ /* response busy check */
|
|
|
case MMC_SWITCH:
|
|
|
case MMC_STOP_TRANSMISSION:
|
|
|
case MMC_SET_WRITE_PROT:
|
|
|
case MMC_CLR_WRITE_PROT:
|
|
|
case MMC_ERASE:
|
|
|
case MMC_GEN_CMD:
|
|
|
- mask = MASK_MRBSYE;
|
|
|
+ mask = MASK_START_CMD | MASK_MRBSYE;
|
|
|
break;
|
|
|
default:
|
|
|
- mask = MASK_MCRSPE;
|
|
|
+ mask = MASK_START_CMD | MASK_MCRSPE;
|
|
|
break;
|
|
|
}
|
|
|
- mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
|
|
|
- MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
|
|
|
- MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
|
|
|
- MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
|
|
|
|
|
|
- if (host->data) {
|
|
|
+ if (mrq->data) {
|
|
|
sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
|
|
|
sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
|
|
|
mrq->data->blksz);
|
|
|
}
|
|
|
- opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
|
|
|
+ opc = sh_mmcif_set_cmd(host, mrq);
|
|
|
|
|
|
sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
|
|
|
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
|
|
@@ -744,80 +850,28 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
|
|
|
/* set cmd */
|
|
|
sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
|
|
|
|
|
|
- time = wait_for_completion_interruptible_timeout(&host->intr_wait,
|
|
|
- host->timeout);
|
|
|
- if (time <= 0) {
|
|
|
- cmd->error = sh_mmcif_error_manage(host);
|
|
|
- return;
|
|
|
- }
|
|
|
- if (host->sd_error) {
|
|
|
- switch (cmd->opcode) {
|
|
|
- case MMC_ALL_SEND_CID:
|
|
|
- case MMC_SELECT_CARD:
|
|
|
- case MMC_APP_CMD:
|
|
|
- cmd->error = -ETIMEDOUT;
|
|
|
- break;
|
|
|
- default:
|
|
|
- dev_dbg(&host->pd->dev, "Cmd(d'%d) err\n",
|
|
|
- cmd->opcode);
|
|
|
- cmd->error = sh_mmcif_error_manage(host);
|
|
|
- break;
|
|
|
- }
|
|
|
- host->sd_error = false;
|
|
|
- return;
|
|
|
- }
|
|
|
- if (!(cmd->flags & MMC_RSP_PRESENT)) {
|
|
|
- cmd->error = 0;
|
|
|
- return;
|
|
|
- }
|
|
|
- sh_mmcif_get_response(host, cmd);
|
|
|
- if (host->data) {
|
|
|
- if (!host->dma_active) {
|
|
|
- ret = sh_mmcif_data_trans(host, mrq, cmd->opcode);
|
|
|
- } else {
|
|
|
- long time =
|
|
|
- wait_for_completion_interruptible_timeout(&host->dma_complete,
|
|
|
- host->timeout);
|
|
|
- if (!time)
|
|
|
- ret = -ETIMEDOUT;
|
|
|
- else if (time < 0)
|
|
|
- ret = time;
|
|
|
- sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
|
|
|
- BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
|
|
|
- host->dma_active = false;
|
|
|
- }
|
|
|
- if (ret < 0)
|
|
|
- mrq->data->bytes_xfered = 0;
|
|
|
- else
|
|
|
- mrq->data->bytes_xfered =
|
|
|
- mrq->data->blocks * mrq->data->blksz;
|
|
|
- }
|
|
|
- cmd->error = ret;
|
|
|
+ host->wait_for = MMCIF_WAIT_FOR_CMD;
|
|
|
+ schedule_delayed_work(&host->timeout_work, host->timeout);
|
|
|
}
|
|
|
|
|
|
static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
|
|
|
- struct mmc_request *mrq, struct mmc_command *cmd)
|
|
|
+ struct mmc_request *mrq)
|
|
|
{
|
|
|
- long time;
|
|
|
-
|
|
|
- if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)
|
|
|
+ switch (mrq->cmd->opcode) {
|
|
|
+ case MMC_READ_MULTIPLE_BLOCK:
|
|
|
sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
|
|
|
- else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
|
|
|
+ break;
|
|
|
+ case MMC_WRITE_MULTIPLE_BLOCK:
|
|
|
sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
|
|
|
- else {
|
|
|
+ break;
|
|
|
+ default:
|
|
|
dev_err(&host->pd->dev, "unsupported stop cmd\n");
|
|
|
- cmd->error = sh_mmcif_error_manage(host);
|
|
|
+ mrq->stop->error = sh_mmcif_error_manage(host);
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
- time = wait_for_completion_interruptible_timeout(&host->intr_wait,
|
|
|
- host->timeout);
|
|
|
- if (time <= 0 || host->sd_error) {
|
|
|
- cmd->error = sh_mmcif_error_manage(host);
|
|
|
- return;
|
|
|
- }
|
|
|
- sh_mmcif_get_cmd12response(host, cmd);
|
|
|
- cmd->error = 0;
|
|
|
+ host->wait_for = MMCIF_WAIT_FOR_STOP;
|
|
|
+ schedule_delayed_work(&host->timeout_work, host->timeout);
|
|
|
}
|
|
|
|
|
|
static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
@@ -856,23 +910,10 @@ static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
|
default:
|
|
|
break;
|
|
|
}
|
|
|
- host->data = mrq->data;
|
|
|
- if (mrq->data) {
|
|
|
- if (mrq->data->flags & MMC_DATA_READ) {
|
|
|
- if (host->chan_rx)
|
|
|
- sh_mmcif_start_dma_rx(host);
|
|
|
- } else {
|
|
|
- if (host->chan_tx)
|
|
|
- sh_mmcif_start_dma_tx(host);
|
|
|
- }
|
|
|
- }
|
|
|
- sh_mmcif_start_cmd(host, mrq, mrq->cmd);
|
|
|
- host->data = NULL;
|
|
|
|
|
|
- if (!mrq->cmd->error && mrq->stop)
|
|
|
- sh_mmcif_stop_cmd(host, mrq, mrq->stop);
|
|
|
- host->state = STATE_IDLE;
|
|
|
- mmc_request_done(mmc, mrq);
|
|
|
+ host->mrq = mrq;
|
|
|
+
|
|
|
+ sh_mmcif_start_cmd(host, mrq);
|
|
|
}
|
|
|
|
|
|
static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
@@ -947,9 +988,156 @@ static struct mmc_host_ops sh_mmcif_ops = {
|
|
|
.get_cd = sh_mmcif_get_cd,
|
|
|
};
|
|
|
|
|
|
-static void sh_mmcif_detect(struct mmc_host *mmc)
|
|
|
+static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
|
|
|
{
|
|
|
- mmc_detect_change(mmc, 0);
|
|
|
+ struct mmc_command *cmd = host->mrq->cmd;
|
|
|
+ struct mmc_data *data = host->mrq->data;
|
|
|
+ long time;
|
|
|
+
|
|
|
+ if (host->sd_error) {
|
|
|
+ switch (cmd->opcode) {
|
|
|
+ case MMC_ALL_SEND_CID:
|
|
|
+ case MMC_SELECT_CARD:
|
|
|
+ case MMC_APP_CMD:
|
|
|
+ cmd->error = -ETIMEDOUT;
|
|
|
+ host->sd_error = false;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ cmd->error = sh_mmcif_error_manage(host);
|
|
|
+ dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n",
|
|
|
+ cmd->opcode, cmd->error);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ return false;
|
|
|
+ }
|
|
|
+ if (!(cmd->flags & MMC_RSP_PRESENT)) {
|
|
|
+ cmd->error = 0;
|
|
|
+ return false;
|
|
|
+ }
|
|
|
+
|
|
|
+ sh_mmcif_get_response(host, cmd);
|
|
|
+
|
|
|
+ if (!data)
|
|
|
+ return false;
|
|
|
+
|
|
|
+ if (data->flags & MMC_DATA_READ) {
|
|
|
+ if (host->chan_rx)
|
|
|
+ sh_mmcif_start_dma_rx(host);
|
|
|
+ } else {
|
|
|
+ if (host->chan_tx)
|
|
|
+ sh_mmcif_start_dma_tx(host);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!host->dma_active) {
|
|
|
+ data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
|
|
|
+ if (!data->error)
|
|
|
+ return true;
|
|
|
+ return false;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Running in the IRQ thread, can sleep */
|
|
|
+ time = wait_for_completion_interruptible_timeout(&host->dma_complete,
|
|
|
+ host->timeout);
|
|
|
+ if (host->sd_error) {
|
|
|
+ dev_err(host->mmc->parent,
|
|
|
+ "Error IRQ while waiting for DMA completion!\n");
|
|
|
+ /* Woken up by an error IRQ: abort DMA */
|
|
|
+ if (data->flags & MMC_DATA_READ)
|
|
|
+ dmaengine_terminate_all(host->chan_rx);
|
|
|
+ else
|
|
|
+ dmaengine_terminate_all(host->chan_tx);
|
|
|
+ data->error = sh_mmcif_error_manage(host);
|
|
|
+ } else if (!time) {
|
|
|
+ data->error = -ETIMEDOUT;
|
|
|
+ } else if (time < 0) {
|
|
|
+ data->error = time;
|
|
|
+ }
|
|
|
+ sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
|
|
|
+ BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
|
|
|
+ host->dma_active = false;
|
|
|
+
|
|
|
+ if (data->error)
|
|
|
+ data->bytes_xfered = 0;
|
|
|
+
|
|
|
+ return false;
|
|
|
+}
|
|
|
+
|
|
|
+static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
|
|
|
+{
|
|
|
+ struct sh_mmcif_host *host = dev_id;
|
|
|
+ struct mmc_request *mrq = host->mrq;
|
|
|
+ struct mmc_data *data = mrq->data;
|
|
|
+
|
|
|
+ cancel_delayed_work_sync(&host->timeout_work);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * All handlers return true, if processing continues, and false, if the
|
|
|
+ * request has to be completed - successfully or not
|
|
|
+ */
|
|
|
+ switch (host->wait_for) {
|
|
|
+ case MMCIF_WAIT_FOR_REQUEST:
|
|
|
+ /* We're too late, the timeout has already kicked in */
|
|
|
+ return IRQ_HANDLED;
|
|
|
+ case MMCIF_WAIT_FOR_CMD:
|
|
|
+ if (sh_mmcif_end_cmd(host))
|
|
|
+ /* Wait for data */
|
|
|
+ return IRQ_HANDLED;
|
|
|
+ break;
|
|
|
+ case MMCIF_WAIT_FOR_MREAD:
|
|
|
+ if (sh_mmcif_mread_block(host))
|
|
|
+ /* Wait for more data */
|
|
|
+ return IRQ_HANDLED;
|
|
|
+ break;
|
|
|
+ case MMCIF_WAIT_FOR_READ:
|
|
|
+ if (sh_mmcif_read_block(host))
|
|
|
+ /* Wait for data end */
|
|
|
+ return IRQ_HANDLED;
|
|
|
+ break;
|
|
|
+ case MMCIF_WAIT_FOR_MWRITE:
|
|
|
+ if (sh_mmcif_mwrite_block(host))
|
|
|
+ /* Wait data to write */
|
|
|
+ return IRQ_HANDLED;
|
|
|
+ break;
|
|
|
+ case MMCIF_WAIT_FOR_WRITE:
|
|
|
+ if (sh_mmcif_write_block(host))
|
|
|
+ /* Wait for data end */
|
|
|
+ return IRQ_HANDLED;
|
|
|
+ break;
|
|
|
+ case MMCIF_WAIT_FOR_STOP:
|
|
|
+ if (host->sd_error) {
|
|
|
+ mrq->stop->error = sh_mmcif_error_manage(host);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ sh_mmcif_get_cmd12response(host, mrq->stop);
|
|
|
+ mrq->stop->error = 0;
|
|
|
+ break;
|
|
|
+ case MMCIF_WAIT_FOR_READ_END:
|
|
|
+ case MMCIF_WAIT_FOR_WRITE_END:
|
|
|
+ if (host->sd_error)
|
|
|
+ data->error = sh_mmcif_error_manage(host);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ BUG();
|
|
|
+ }
|
|
|
+
|
|
|
+ if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
|
|
|
+ if (!mrq->cmd->error && data && !data->error)
|
|
|
+ data->bytes_xfered =
|
|
|
+ data->blocks * data->blksz;
|
|
|
+
|
|
|
+ if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
|
|
|
+ sh_mmcif_stop_cmd(host, mrq);
|
|
|
+ if (!mrq->stop->error)
|
|
|
+ return IRQ_HANDLED;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ host->wait_for = MMCIF_WAIT_FOR_REQUEST;
|
|
|
+ host->state = STATE_IDLE;
|
|
|
+ host->mrq = NULL;
|
|
|
+ mmc_request_done(host->mmc, mrq);
|
|
|
+
|
|
|
+ return IRQ_HANDLED;
|
|
|
}
|
|
|
|
|
|
static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
|
|
@@ -960,7 +1148,12 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
|
|
|
|
|
|
state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
|
|
|
|
|
|
- if (state & INT_RBSYE) {
|
|
|
+ if (state & INT_ERR_STS) {
|
|
|
+ /* error interrupts - process first */
|
|
|
+ sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
|
|
|
+ sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
|
|
|
+ err = 1;
|
|
|
+ } else if (state & INT_RBSYE) {
|
|
|
sh_mmcif_writel(host->addr, MMCIF_CE_INT,
|
|
|
~(INT_RBSYE | INT_CRSPE));
|
|
|
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
|
|
@@ -988,11 +1181,6 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
|
|
|
sh_mmcif_writel(host->addr, MMCIF_CE_INT,
|
|
|
~(INT_CMD12RBE | INT_CMD12CRE));
|
|
|
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
|
|
|
- } else if (state & INT_ERR_STS) {
|
|
|
- /* err interrupts */
|
|
|
- sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
|
|
|
- sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
|
|
|
- err = 1;
|
|
|
} else {
|
|
|
dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
|
|
|
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
|
|
@@ -1003,14 +1191,57 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
|
|
|
host->sd_error = true;
|
|
|
dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
|
|
|
}
|
|
|
- if (state & ~(INT_CMD12RBE | INT_CMD12CRE))
|
|
|
- complete(&host->intr_wait);
|
|
|
- else
|
|
|
+ if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
|
|
|
+ if (!host->dma_active)
|
|
|
+ return IRQ_WAKE_THREAD;
|
|
|
+ else if (host->sd_error)
|
|
|
+ mmcif_dma_complete(host);
|
|
|
+ } else {
|
|
|
dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
|
|
|
+ }
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
}
|
|
|
|
|
|
+static void mmcif_timeout_work(struct work_struct *work)
|
|
|
+{
|
|
|
+ struct delayed_work *d = container_of(work, struct delayed_work, work);
|
|
|
+ struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
|
|
|
+ struct mmc_request *mrq = host->mrq;
|
|
|
+
|
|
|
+ if (host->dying)
|
|
|
+ /* Don't run after mmc_remove_host() */
|
|
|
+ return;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Handle races with cancel_delayed_work(), unless
|
|
|
+ * cancel_delayed_work_sync() is used
|
|
|
+ */
|
|
|
+ switch (host->wait_for) {
|
|
|
+ case MMCIF_WAIT_FOR_CMD:
|
|
|
+ mrq->cmd->error = sh_mmcif_error_manage(host);
|
|
|
+ break;
|
|
|
+ case MMCIF_WAIT_FOR_STOP:
|
|
|
+ mrq->stop->error = sh_mmcif_error_manage(host);
|
|
|
+ break;
|
|
|
+ case MMCIF_WAIT_FOR_MREAD:
|
|
|
+ case MMCIF_WAIT_FOR_MWRITE:
|
|
|
+ case MMCIF_WAIT_FOR_READ:
|
|
|
+ case MMCIF_WAIT_FOR_WRITE:
|
|
|
+ case MMCIF_WAIT_FOR_READ_END:
|
|
|
+ case MMCIF_WAIT_FOR_WRITE_END:
|
|
|
+ mrq->data->error = sh_mmcif_error_manage(host);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ BUG();
|
|
|
+ }
|
|
|
+
|
|
|
+ host->state = STATE_IDLE;
|
|
|
+ host->wait_for = MMCIF_WAIT_FOR_REQUEST;
|
|
|
+ host->mrq = NULL;
|
|
|
+ mmc_request_done(host->mmc, mrq);
|
|
|
+}
|
|
|
+
|
|
|
static int __devinit sh_mmcif_probe(struct platform_device *pdev)
|
|
|
{
|
|
|
int ret = 0, irq[2];
|
|
@@ -1064,7 +1295,6 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
|
|
|
host->clk = clk_get_rate(host->hclk);
|
|
|
host->pd = pdev;
|
|
|
|
|
|
- init_completion(&host->intr_wait);
|
|
|
spin_lock_init(&host->lock);
|
|
|
|
|
|
mmc->ops = &sh_mmcif_ops;
|
|
@@ -1101,19 +1331,21 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
|
|
|
|
|
|
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
|
|
|
|
|
|
- ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host);
|
|
|
+ ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host);
|
|
|
if (ret) {
|
|
|
dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
|
|
|
goto clean_up3;
|
|
|
}
|
|
|
- ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host);
|
|
|
+ ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host);
|
|
|
if (ret) {
|
|
|
free_irq(irq[0], host);
|
|
|
dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
|
|
|
goto clean_up3;
|
|
|
}
|
|
|
|
|
|
- sh_mmcif_detect(host->mmc);
|
|
|
+ INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
|
|
|
+
|
|
|
+ mmc_detect_change(host->mmc, 0);
|
|
|
|
|
|
dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
|
|
|
dev_dbg(&pdev->dev, "chip ver H'%04x\n",
|
|
@@ -1139,11 +1371,19 @@ static int __devexit sh_mmcif_remove(struct platform_device *pdev)
|
|
|
struct sh_mmcif_host *host = platform_get_drvdata(pdev);
|
|
|
int irq[2];
|
|
|
|
|
|
+ host->dying = true;
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
|
|
mmc_remove_host(host->mmc);
|
|
|
sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
|
|
|
|
|
|
+ /*
|
|
|
+ * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
|
|
|
+ * mmc_remove_host() call above. But swapping order doesn't help either
|
|
|
+ * (a query on the linux-mmc mailing list didn't bring any replies).
|
|
|
+ */
|
|
|
+ cancel_delayed_work_sync(&host->timeout_work);
|
|
|
+
|
|
|
if (host->addr)
|
|
|
iounmap(host->addr);
|
|
|
|
|
@@ -1206,19 +1446,7 @@ static struct platform_driver sh_mmcif_driver = {
|
|
|
},
|
|
|
};
|
|
|
|
|
|
-static int __init sh_mmcif_init(void)
|
|
|
-{
|
|
|
- return platform_driver_register(&sh_mmcif_driver);
|
|
|
-}
|
|
|
-
|
|
|
-static void __exit sh_mmcif_exit(void)
|
|
|
-{
|
|
|
- platform_driver_unregister(&sh_mmcif_driver);
|
|
|
-}
|
|
|
-
|
|
|
-module_init(sh_mmcif_init);
|
|
|
-module_exit(sh_mmcif_exit);
|
|
|
-
|
|
|
+module_platform_driver(sh_mmcif_driver);
|
|
|
|
|
|
MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
|
|
|
MODULE_LICENSE("GPL");
|