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@@ -409,22 +409,32 @@ static int i915_pmu_event_init(struct perf_event *event)
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return 0;
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}
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-static u64 get_rc6(struct drm_i915_private *i915, bool locked)
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+static u64 __get_rc6(struct drm_i915_private *i915)
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{
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- unsigned long flags;
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u64 val;
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- if (intel_runtime_pm_get_if_in_use(i915)) {
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- val = intel_rc6_residency_ns(i915, IS_VALLEYVIEW(i915) ?
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- VLV_GT_RENDER_RC6 :
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- GEN6_GT_GFX_RC6);
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+ val = intel_rc6_residency_ns(i915,
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+ IS_VALLEYVIEW(i915) ?
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+ VLV_GT_RENDER_RC6 :
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+ GEN6_GT_GFX_RC6);
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- if (HAS_RC6p(i915))
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- val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
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+ if (HAS_RC6p(i915))
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+ val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
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+
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+ if (HAS_RC6pp(i915))
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+ val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
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+
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+ return val;
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+}
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- if (HAS_RC6pp(i915))
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- val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
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+static u64 get_rc6(struct drm_i915_private *i915, bool locked)
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+{
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+#if IS_ENABLED(CONFIG_PM)
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+ unsigned long flags;
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+ u64 val;
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+ if (intel_runtime_pm_get_if_in_use(i915)) {
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+ val = __get_rc6(i915);
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intel_runtime_pm_put(i915);
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/*
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@@ -481,6 +491,9 @@ static u64 get_rc6(struct drm_i915_private *i915, bool locked)
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}
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return val;
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+#else
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+ return __get_rc6(i915);
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+#endif
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}
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static u64 __i915_pmu_event_read(struct perf_event *event, bool locked)
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