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@@ -29,6 +29,7 @@
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#define SCLK_SDMMC 68
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#define SCLK_SDMMC 68
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#define SCLK_SDIO 69
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#define SCLK_SDIO 69
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#define SCLK_EMMC 71
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#define SCLK_EMMC 71
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+#define SCLK_TSADC 72
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#define SCLK_UART0 77
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#define SCLK_UART0 77
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#define SCLK_UART1 78
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#define SCLK_UART1 78
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#define SCLK_UART2 79
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#define SCLK_UART2 79
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@@ -49,10 +50,17 @@
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#define SCLK_SDMMC_SAMPLE 118
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#define SCLK_SDMMC_SAMPLE 118
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#define SCLK_SDIO_SAMPLE 119
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#define SCLK_SDIO_SAMPLE 119
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#define SCLK_EMMC_SAMPLE 121
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#define SCLK_EMMC_SAMPLE 121
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+#define SCLK_VOP 122
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+#define SCLK_HDMI_HDCP 123
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+
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+/* dclk gates */
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+#define DCLK_VOP 190
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+#define DCLK_HDMI_PHY 191
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/* aclk gates */
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/* aclk gates */
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#define ACLK_DMAC 194
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#define ACLK_DMAC 194
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#define ACLK_PERI 210
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#define ACLK_PERI 210
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+#define ACLK_VOP 211
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/* pclk gates */
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/* pclk gates */
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#define PCLK_GPIO0 320
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#define PCLK_GPIO0 320
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@@ -68,11 +76,15 @@
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#define PCLK_UART0 341
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#define PCLK_UART0 341
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#define PCLK_UART1 342
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#define PCLK_UART1 342
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#define PCLK_UART2 343
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#define PCLK_UART2 343
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+#define PCLK_TSADC 344
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#define PCLK_PWM 350
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#define PCLK_PWM 350
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#define PCLK_TIMER 353
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#define PCLK_TIMER 353
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#define PCLK_PERI 363
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#define PCLK_PERI 363
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+#define PCLK_HDMI_CTRL 364
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+#define PCLK_HDMI_PHY 365
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/* hclk gates */
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/* hclk gates */
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+#define HCLK_VOP 452
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#define HCLK_NANDC 453
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#define HCLK_NANDC 453
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#define HCLK_SDMMC 456
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#define HCLK_SDMMC 456
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#define HCLK_SDIO 457
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#define HCLK_SDIO 457
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Heiko Stuebner