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@@ -150,7 +150,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
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u32 stride_reg = vgpu_vreg(vgpu, DSPSTRIDE(pipe)) & stride_mask;
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u32 stride = stride_reg;
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- if (IS_SKYLAKE(dev_priv)) {
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+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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switch (tiled) {
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case PLANE_CTL_TILED_LINEAR:
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stride = stride_reg * 64;
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@@ -214,7 +214,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
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if (!plane->enabled)
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return -ENODEV;
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- if (IS_SKYLAKE(dev_priv)) {
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+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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plane->tiled = (val & PLANE_CTL_TILED_MASK) >>
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_PLANE_CTL_TILED_SHIFT;
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fmt = skl_format_to_drm(
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@@ -253,8 +253,9 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
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}
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plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10),
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- (IS_SKYLAKE(dev_priv)) ? (_PRI_PLANE_STRIDE_MASK >> 6) :
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- _PRI_PLANE_STRIDE_MASK, plane->bpp);
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+ (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) ?
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+ (_PRI_PLANE_STRIDE_MASK >> 6) :
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+ _PRI_PLANE_STRIDE_MASK, plane->bpp);
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plane->width = (vgpu_vreg(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
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_PIPE_H_SRCSZ_SHIFT;
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