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@@ -94,6 +94,7 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
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const struct drm_display_mode *mode = &cstate->mode;
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const struct drm_display_mode *mode = &cstate->mode;
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struct drm_framebuffer *fb = plane->state->fb;
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struct drm_framebuffer *fb = plane->state->fb;
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struct drm_connector *connector = priv->connector;
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struct drm_connector *connector = priv->connector;
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+ struct drm_bridge *bridge = priv->bridge;
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u32 cntl;
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u32 cntl;
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u32 ppl, hsw, hfp, hbp;
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u32 ppl, hsw, hfp, hbp;
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u32 lpp, vsw, vfp, vbp;
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u32 lpp, vsw, vfp, vbp;
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@@ -143,11 +144,37 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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tim2 |= TIM2_IVS;
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tim2 |= TIM2_IVS;
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- if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
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- tim2 |= TIM2_IOE;
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+ if (connector) {
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+ if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
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+ tim2 |= TIM2_IOE;
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- if (connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
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- tim2 |= TIM2_IPC;
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+ if (connector->display_info.bus_flags &
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+ DRM_BUS_FLAG_PIXDATA_NEGEDGE)
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+ tim2 |= TIM2_IPC;
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+ }
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+
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+ if (bridge) {
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+ const struct drm_bridge_timings *btimings = bridge->timings;
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+
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+ /*
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+ * Here is when things get really fun. Sometimes the bridge
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+ * timings are such that the signal out from PL11x is not
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+ * stable before the receiving bridge (such as a dumb VGA DAC
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+ * or similar) samples it. If that happens, we compensate by
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+ * the only method we have: output the data on the opposite
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+ * edge of the clock so it is for sure stable when it gets
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+ * sampled.
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+ *
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+ * The PL111 manual does not contain proper timining diagrams
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+ * or data for these details, but we know from experiments
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+ * that the setup time is more than 3000 picoseconds (3 ns).
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+ * If we have a bridge that requires the signal to be stable
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+ * earlier than 3000 ps before the clock pulse, we have to
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+ * output the data on the opposite edge to avoid flicker.
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+ */
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+ if (btimings && btimings->setup_time_ps >= 3000)
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+ tim2 ^= TIM2_IPC;
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+ }
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tim2 |= cpl << 16;
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tim2 |= cpl << 16;
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writel(tim2, priv->regs + CLCD_TIM2);
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writel(tim2, priv->regs + CLCD_TIM2);
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