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@@ -231,6 +231,7 @@ u8 rv770_get_seq_value(struct radeon_device *rdev,
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MC_CG_SEQ_DRAMCONF_S0 : MC_CG_SEQ_DRAMCONF_S1;
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}
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+#if 0
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int rv770_read_smc_soft_register(struct radeon_device *rdev,
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u16 reg_offset, u32 *value)
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{
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@@ -240,6 +241,7 @@ int rv770_read_smc_soft_register(struct radeon_device *rdev,
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pi->soft_regs_start + reg_offset,
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value, pi->sram_end);
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}
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+#endif
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int rv770_write_smc_soft_register(struct radeon_device *rdev,
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u16 reg_offset, u32 value)
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@@ -2075,6 +2077,7 @@ int rv770_dpm_set_power_state(struct radeon_device *rdev)
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return 0;
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}
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+#if 0
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void rv770_dpm_reset_asic(struct radeon_device *rdev)
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{
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struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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@@ -2087,6 +2090,7 @@ void rv770_dpm_reset_asic(struct radeon_device *rdev)
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if (pi->dcodt)
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rv770_program_dcodt_after_state_switch(rdev, boot_ps, boot_ps);
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}
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+#endif
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void rv770_dpm_setup_asic(struct radeon_device *rdev)
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{
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