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@@ -66,8 +66,14 @@
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#define PIPE_REG_COMMAND 0x00 /* write: value = command */
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#define PIPE_REG_STATUS 0x04 /* read */
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#define PIPE_REG_CHANNEL 0x08 /* read/write: channel id */
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+#ifdef CONFIG_64BIT
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+#define PIPE_REG_CHANNEL_HIGH 0x30 /* read/write: channel id */
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+#endif
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#define PIPE_REG_SIZE 0x0c /* read/write: buffer size */
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#define PIPE_REG_ADDRESS 0x10 /* write: physical address */
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+#ifdef CONFIG_64BIT
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+#define PIPE_REG_ADDRESS_HIGH 0x34 /* write: physical address */
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+#endif
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#define PIPE_REG_WAKES 0x14 /* read: wake flags */
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#define PIPE_REG_PARAMS_ADDR_LOW 0x18 /* read/write: batch data address */
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#define PIPE_REG_PARAMS_ADDR_HIGH 0x1c /* read/write: batch data address */
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@@ -109,9 +115,9 @@
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#define PIPE_WAKE_WRITE (1 << 2) /* pipe can now be written to */
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struct access_params {
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- u32 channel;
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+ unsigned long channel;
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u32 size;
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- u32 address;
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+ unsigned long address;
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u32 cmd;
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u32 result;
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/* reserved for future extension */
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@@ -155,7 +161,10 @@ static u32 goldfish_cmd_status(struct goldfish_pipe *pipe, u32 cmd)
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struct goldfish_pipe_dev *dev = pipe->dev;
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spin_lock_irqsave(&dev->lock, flags);
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- writel((u32)pipe, dev->base + PIPE_REG_CHANNEL);
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+ writel((u32)(u64)pipe, dev->base + PIPE_REG_CHANNEL);
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+#ifdef CONFIG_64BIT
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+ writel((u32)((u64)pipe >> 32), dev->base + PIPE_REG_CHANNEL_HIGH);
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+#endif
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writel(cmd, dev->base + PIPE_REG_COMMAND);
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status = readl(dev->base + PIPE_REG_STATUS);
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spin_unlock_irqrestore(&dev->lock, flags);
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@@ -168,7 +177,10 @@ static void goldfish_cmd(struct goldfish_pipe *pipe, u32 cmd)
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struct goldfish_pipe_dev *dev = pipe->dev;
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spin_lock_irqsave(&dev->lock, flags);
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- writel((u32)pipe, dev->base + PIPE_REG_CHANNEL);
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+ writel((u32)(u64)pipe, dev->base + PIPE_REG_CHANNEL);
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+#ifdef CONFIG_64BIT
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+ writel((u32)((u64)pipe >> 32), dev->base + PIPE_REG_CHANNEL_HIGH);
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+#endif
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writel(cmd, dev->base + PIPE_REG_COMMAND);
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spin_unlock_irqrestore(&dev->lock, flags);
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}
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@@ -322,9 +334,15 @@ static ssize_t goldfish_pipe_read_write(struct file *filp, char __user *buffer,
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spin_lock_irqsave(&dev->lock, irq_flags);
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if (access_with_param(dev, CMD_WRITE_BUFFER + cmd_offset,
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address, avail, pipe, &status)) {
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- writel((u32)pipe, dev->base + PIPE_REG_CHANNEL);
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+ writel((u32)(u64)pipe, dev->base + PIPE_REG_CHANNEL);
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+#ifdef CONFIG_64BIT
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+ writel((u32)((u64)pipe >> 32), dev->base + PIPE_REG_CHANNEL_HIGH);
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+#endif
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writel(avail, dev->base + PIPE_REG_SIZE);
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writel(address, dev->base + PIPE_REG_ADDRESS);
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+#ifdef CONFIG_64BIT
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+ writel((u32)((u64)address >> 32), dev->base + PIPE_REG_ADDRESS_HIGH);
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+#endif
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writel(CMD_WRITE_BUFFER + cmd_offset,
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dev->base + PIPE_REG_COMMAND);
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status = readl(dev->base + PIPE_REG_STATUS);
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@@ -447,7 +465,12 @@ static irqreturn_t goldfish_pipe_interrupt(int irq, void *dev_id)
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/* First read the channel, 0 means the end of the list */
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struct goldfish_pipe *pipe;
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unsigned long wakes;
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- unsigned long channel = readl(dev->base + PIPE_REG_CHANNEL);
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+ unsigned long channel = 0;
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+
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+#ifdef CONFIG_64BIT
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+ channel = (u64)readl(dev->base + PIPE_REG_CHANNEL_HIGH) << 32;
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+#endif
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+ channel |= readl(dev->base + PIPE_REG_CHANNEL);
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if (channel == 0)
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break;
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